OASIS-8C System
をテンプレートにして作成
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開始行:
CENTER:SIZE(60){COLOR(gold){OASIS-8C Processor of FPGA}}
*Project Goal [#f1f26636]
- Real design in verilog HDL and prototyping on FPGA of a...
- [[Detailed Design Manual>http://aslweb.u-aizu.ac.jp/asl...
-Target Application: Image Recognition
***Members [#vc808259]
- Prof. Okuyama
-[[D1 Nam Khanh Dang>Nam K. Dang]] (d8162103)
-[[B4 Akihito Kajikawa(???? ???)>Akihito Kajikawa]] (s120...
-[[B3 Ryunosuke Murakami(¼?? ζǷ??)>Ryunosuke Murakami]] (...
-[[B3 Kaori Yatsu(ë?? ??)>Kaori Yatsu]] (s1210103)
-[[B3 Nao Miyamoto(???? ???)>Nao Miyamoto]] (s1210060)
-[[B3 Hiroki Yomogita(˩?? ?絮)>Hiroki Yomogita]] (s1210042)
-[[B3 Yuji Murakami(¼?? ?һ?)>Yuji Murakami]] (s1210019)
-[[B3 Kota Toyama(???? ????)>Kota Toyama]] (s1210201)
-[[B3 Yuga Inoue(???ͥ??)>Yuga Inoue]] (s1210087)
*System Architecture [#e31ae400]
- 2x2x2 Network-on-Chip:
CENTER:[[&ref(top-level2.png,,60%);>http://aslweb.u-aizu....
- Network's PE:
CENTER:[[&ref(tile-diagram.png,,60%);>http://aslweb.u-aiz...
*Specification [#j83a3824]
- System specifications:
-- OASIS 3D Network-on-Chip [[[Ref.1]>http://aslweb.u-aiz...
--- Topology: 3D Mesh.
--- Network's Size: 2x2x2.
--- Document & source code: [[[Ref.1]>http://aslweb.u-aiz...
-- Network Interface: [[[Ref.2]>http://aslweb.u-aizu.ac.j...
-- Processing Elements: COLOR(red){(TBD)}
--- CPU: MIPS
--- MEM: On-chip (verilog code), Off-chip (see I/O).
--- I/O: Off-chip Memory, Display (LCD, LED), Inter-conne...
- Application specifications:COLOR(red){(TBD)}
-- Target CPU: MIPS.
-- Target applications: Image processing (filtering).
- Implementation environment:
-- Language: Verilog HDL.
-- Simulation tool: Modelsim Altera/Cadence Tools.
-- Implementation tool: Altera Quartus II/ASIC.
- Implementation board: Spartan DE II/CMOS 45 nm.
*Hardware Prototyping Tasks [#k85f0a2d]
- Task 01: Processor Implemenation [[(manual)>http://aslw...
-- Understading the Processor architecture and operation.
-- Implementation of I/O accessing operation.
-- Simulation and implemenation.
- Task 02: Network-Interface Implemenation [[(manual)>htt...
-- Establishing an individual network tile: PE(Processing...
-- Implemenation local interfacing.
-- Implementation on FPGA/ASIC.
- Task 03: Network Implementation [[(manual)>http://aslwe...
-- Establish a 2D 2x2x2 Network Implementation.
-- Network simulation.
-- Implementation on FPGA/ASIC.
- Task 04: Application Implementation [[(manual)>http://a...
-- Establishing the algorithm base on network's architect...
-- Application demonstration.
*Schedule [#y16f9bb9]
- Detail of schedule
|COLOR(blue){Step}|COLOR(blue){Content}|COLOR(blue){Start...
|1|COLOR(green){Design Preparation}|2015-June-02|2015-Jun...
|2|Group first meeting |2015-July-17|2015-July-17||
|3|Group meeting |COLOR(red){2015-Aug-10}|2015-Aug-10||
|4|Group meeting |COLOR(red){2015-Sep-28}|2015-Sep-28||
- Task Assignment (Step 02)
|COLOR(blue){No.}|COLOR(blue){Assignee}|COLOR(blue){Task}...
|1|Khanh|COLOR(green){Prepare the schedule of the Project...
|2.1|H.Yomogita, Y.Inoue|Processor Implemenation|2015-09-...
|2.2|R.Murakami, K.Toyama|Network-Interface Implemenation...
|2.3|Y.Murakami |Network Implementation|2015-09-28|-|
|2.4|N.Miyamoto, K.Yatsu|Application Implementation|2015-...
*References [#x829e368]
- [Ref.1]: OASIS Network-on-Chip, Akram Ben Ahmed, [[Inte...
- [Ref.2]: Network Inteface, R. Okada, [[Internal-link>ht...
- [Ref.3]: FPGA manual (TBU).
- [Ref.4]: MIPS_MultiCycle.zip : file://///zxw001/PUBLIC/...
----
Last Update:
- 2015 June 8th: Update system architecture diagram.
終了行:
CENTER:SIZE(60){COLOR(gold){OASIS-8C Processor of FPGA}}
*Project Goal [#f1f26636]
- Real design in verilog HDL and prototyping on FPGA of a...
- [[Detailed Design Manual>http://aslweb.u-aizu.ac.jp/asl...
-Target Application: Image Recognition
***Members [#vc808259]
- Prof. Okuyama
-[[D1 Nam Khanh Dang>Nam K. Dang]] (d8162103)
-[[B4 Akihito Kajikawa(???? ???)>Akihito Kajikawa]] (s120...
-[[B3 Ryunosuke Murakami(¼?? ζǷ??)>Ryunosuke Murakami]] (...
-[[B3 Kaori Yatsu(ë?? ??)>Kaori Yatsu]] (s1210103)
-[[B3 Nao Miyamoto(???? ???)>Nao Miyamoto]] (s1210060)
-[[B3 Hiroki Yomogita(˩?? ?絮)>Hiroki Yomogita]] (s1210042)
-[[B3 Yuji Murakami(¼?? ?һ?)>Yuji Murakami]] (s1210019)
-[[B3 Kota Toyama(???? ????)>Kota Toyama]] (s1210201)
-[[B3 Yuga Inoue(???ͥ??)>Yuga Inoue]] (s1210087)
*System Architecture [#e31ae400]
- 2x2x2 Network-on-Chip:
CENTER:[[&ref(top-level2.png,,60%);>http://aslweb.u-aizu....
- Network's PE:
CENTER:[[&ref(tile-diagram.png,,60%);>http://aslweb.u-aiz...
*Specification [#j83a3824]
- System specifications:
-- OASIS 3D Network-on-Chip [[[Ref.1]>http://aslweb.u-aiz...
--- Topology: 3D Mesh.
--- Network's Size: 2x2x2.
--- Document & source code: [[[Ref.1]>http://aslweb.u-aiz...
-- Network Interface: [[[Ref.2]>http://aslweb.u-aizu.ac.j...
-- Processing Elements: COLOR(red){(TBD)}
--- CPU: MIPS
--- MEM: On-chip (verilog code), Off-chip (see I/O).
--- I/O: Off-chip Memory, Display (LCD, LED), Inter-conne...
- Application specifications:COLOR(red){(TBD)}
-- Target CPU: MIPS.
-- Target applications: Image processing (filtering).
- Implementation environment:
-- Language: Verilog HDL.
-- Simulation tool: Modelsim Altera/Cadence Tools.
-- Implementation tool: Altera Quartus II/ASIC.
- Implementation board: Spartan DE II/CMOS 45 nm.
*Hardware Prototyping Tasks [#k85f0a2d]
- Task 01: Processor Implemenation [[(manual)>http://aslw...
-- Understading the Processor architecture and operation.
-- Implementation of I/O accessing operation.
-- Simulation and implemenation.
- Task 02: Network-Interface Implemenation [[(manual)>htt...
-- Establishing an individual network tile: PE(Processing...
-- Implemenation local interfacing.
-- Implementation on FPGA/ASIC.
- Task 03: Network Implementation [[(manual)>http://aslwe...
-- Establish a 2D 2x2x2 Network Implementation.
-- Network simulation.
-- Implementation on FPGA/ASIC.
- Task 04: Application Implementation [[(manual)>http://a...
-- Establishing the algorithm base on network's architect...
-- Application demonstration.
*Schedule [#y16f9bb9]
- Detail of schedule
|COLOR(blue){Step}|COLOR(blue){Content}|COLOR(blue){Start...
|1|COLOR(green){Design Preparation}|2015-June-02|2015-Jun...
|2|Group first meeting |2015-July-17|2015-July-17||
|3|Group meeting |COLOR(red){2015-Aug-10}|2015-Aug-10||
|4|Group meeting |COLOR(red){2015-Sep-28}|2015-Sep-28||
- Task Assignment (Step 02)
|COLOR(blue){No.}|COLOR(blue){Assignee}|COLOR(blue){Task}...
|1|Khanh|COLOR(green){Prepare the schedule of the Project...
|2.1|H.Yomogita, Y.Inoue|Processor Implemenation|2015-09-...
|2.2|R.Murakami, K.Toyama|Network-Interface Implemenation...
|2.3|Y.Murakami |Network Implementation|2015-09-28|-|
|2.4|N.Miyamoto, K.Yatsu|Application Implementation|2015-...
*References [#x829e368]
- [Ref.1]: OASIS Network-on-Chip, Akram Ben Ahmed, [[Inte...
- [Ref.2]: Network Inteface, R. Okada, [[Internal-link>ht...
- [Ref.3]: FPGA manual (TBU).
- [Ref.4]: MIPS_MultiCycle.zip : file://///zxw001/PUBLIC/...
----
Last Update:
- 2015 June 8th: Update system architecture diagram.
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