Mitsuhiro Nakamura
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[[Members-Internal]]
CENTER:SIZE(60){COLOR(#990199){Design and Evaluation of 2...
*Background [#nec7d6fe]
????軻??ή???ϳؤʤɤΥ???ԥ塼???ʳؤˤ????ƽ??פʷ??Ǥ??롣~
????????NxN????ξ軻?ˤ?N3??Ȥ?????????̤η???ɬ?פȤʤ롣~
?????ǹ???軻???Ѳ?ϩ??MatrixProcessor????Ƥ??줿??~
???Υץ????å???PE(Processing Element)?Ȥ????????§Ū???¤٤???¤...
?ޤ??????Υץ????å???PE??ǰ??٤˷????????????ǿ??????䤹???Ȥ????...
*Problem[#mec7d6fe]
????ԥ塼???ʳؤι?????ǻ??Ѥ?????????礭????????Ǥ??ꡢ???ι??????...
????????PE?ο??????ä???ϩ???Ϥ????礹??ȡ???ϩ????»?????Ψ????ޤ...
*Solution[#mec7d6fe]
???????θ???Τ???ˡ??Ѿ㳲??(Fault tolerant)?????????롼?????Ѥ?...
*Research goal[#mec7d6fe]
?????2D-NoC Matrix Processor???????????ǽ?ȿ???????ɾ??????
Design and Evaluation of 2D-OASIS-NoC Matrix Processor
*Research Workflow [#nec7d6fe]
Step1.SN/X + Matrix Processor(COLOR(red){9/29 finish})~
Step2.SN/X + Matrix Processor + Network Interface(COLOR(r...
Step3.SN/X + Matrix Processor + Network Interface + Fault...
Step4.NoC????~
Step5.ɾ??~
*Papers, Theses [#nec7d6fe]
-1. Akram Ben Ahmed, A. Ben Abdallah, ''LA-XYZ: Low Laten...
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?...
-2. [[OASIS-NoC Benchmark suite>http://webfs-int.u-aizu.a...
-3. [[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu....
-4. [[OASIS 3D-Router Physical Design>http://web-ext.u-ai...
-5. R. Okada, A. Ben Abdallah,Architecture and Design of ...
-6 A. Ben Ahmed, On the Design of a 3D Network-on-Chip fo...
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/thes...
-7. [[About TSV: Physical design of a 3D router: reducing...
[[3D-Matrix Processor>3D-Matrix Processor]]
終了行:
[[Members-Internal]]
CENTER:SIZE(60){COLOR(#990199){Design and Evaluation of 2...
*Background [#nec7d6fe]
????軻??ή???ϳؤʤɤΥ???ԥ塼???ʳؤˤ????ƽ??פʷ??Ǥ??롣~
????????NxN????ξ軻?ˤ?N3??Ȥ?????????̤η???ɬ?פȤʤ롣~
?????ǹ???軻???Ѳ?ϩ??MatrixProcessor????Ƥ??줿??~
???Υץ????å???PE(Processing Element)?Ȥ????????§Ū???¤٤???¤...
?ޤ??????Υץ????å???PE??ǰ??٤˷????????????ǿ??????䤹???Ȥ????...
*Problem[#mec7d6fe]
????ԥ塼???ʳؤι?????ǻ??Ѥ?????????礭????????Ǥ??ꡢ???ι??????...
????????PE?ο??????ä???ϩ???Ϥ????礹??ȡ???ϩ????»?????Ψ????ޤ...
*Solution[#mec7d6fe]
???????θ???Τ???ˡ??Ѿ㳲??(Fault tolerant)?????????롼?????Ѥ?...
*Research goal[#mec7d6fe]
?????2D-NoC Matrix Processor???????????ǽ?ȿ???????ɾ??????
Design and Evaluation of 2D-OASIS-NoC Matrix Processor
*Research Workflow [#nec7d6fe]
Step1.SN/X + Matrix Processor(COLOR(red){9/29 finish})~
Step2.SN/X + Matrix Processor + Network Interface(COLOR(r...
Step3.SN/X + Matrix Processor + Network Interface + Fault...
Step4.NoC????~
Step5.ɾ??~
*Papers, Theses [#nec7d6fe]
-1. Akram Ben Ahmed, A. Ben Abdallah, ''LA-XYZ: Low Laten...
[[[DOI>http://ieeexplore.ieee.org/xpl/articleDetails.jsp?...
-2. [[OASIS-NoC Benchmark suite>http://webfs-int.u-aizu.a...
-3. [[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu....
-4. [[OASIS 3D-Router Physical Design>http://web-ext.u-ai...
-5. R. Okada, A. Ben Abdallah,Architecture and Design of ...
-6 A. Ben Ahmed, On the Design of a 3D Network-on-Chip fo...
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/thes...
-7. [[About TSV: Physical design of a 3D router: reducing...
[[3D-Matrix Processor>3D-Matrix Processor]]
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