M1 Akihito Kajikawa
をテンプレートにして作成
[
トップ
] [
新規
|
一覧
|
検索
|
最終更新
|
ヘルプ
]
開始行:
CENTER:SIZE(40){COLOR(green){Design and Evaluation of 4x4...
----
-[[OASIS-VP]]
-[[Members-Internal]]
----
*Research Background [#c8cb61ac]
?ޥ??????ץ????å??οʲ??ˤ?äơ?????Ū?ʻ?Х????ƥ?ؤ????????? ?ƥ??...
*Research Goal [#a900f83d]
Design and Evaluation of 4x4 Mesh-based NoC [for Real-tim...
*Research Schedule [#y6a3002b]
***Step 1 (Finished) [#u6b962a1]
-Design and evaluation of a single Router
***Step 2 [#n84ecc4d] COLOR(blue){January 31, 2017} [#g69...
-Design of a 4x4 OASIS NoC (without PEs)
-Study the complexity, bandwidth, and Latency
***Step 3 COLOR(blue){February 28, 2017} [#g7a4a8a7]
-Investigate and study SIFT Algorithm
--''Reference'': [[SIFT Algorithm (in Japanese)>https://d...
***Step 4 COLOR(blue){April 30, 2017} [#z3d05ba1]
-Investigate SIFT Task Graph
-Investigate suitable PEs
-Investigate required hardware configuration
***Step 5 COLOR(blue){June 30, 2017} [#tdb0e927]
-Use Step 2 and integrate PEs, Memory, and NI.
***Step 5 COLOR(blue){September 30, 2017} [#e0b77ff3]
-Evaluate the performance of the system.
***Step 5 COLOR(blue){November 30, 2017} [#qc91854a]
-Debugging
***Step 5 COLOR(blue){December 15 - Janury 8, 2018} [#x65...
-Write MS thesis
*References [#ba027dbf]
-[[GT>Akihito Kajikawa]]
- Main references: Japanese spec: https://github.com/open...
-[[Small MIPS Processor in Verilog>https://drive.google.c...
-Other Links
--[[OASIS-VP GDoc Spec (editable)>https://docs.google.com...
--[[SIFT Lecture (Video)>https://www.youtube.com/watch?v=...
--[[SIFT Lecture (Japanese)>https://drive.google.com/file...
--[[SIFT Demo (Matlab)>https://drive.google.com/file/d/0B...
--[[Tapeout (by Akram)>https://drive.google.com/file/d/0B...
終了行:
CENTER:SIZE(40){COLOR(green){Design and Evaluation of 4x4...
----
-[[OASIS-VP]]
-[[Members-Internal]]
----
*Research Background [#c8cb61ac]
?ޥ??????ץ????å??οʲ??ˤ?äơ?????Ū?ʻ?Х????ƥ?ؤ????????? ?ƥ??...
*Research Goal [#a900f83d]
Design and Evaluation of 4x4 Mesh-based NoC [for Real-tim...
*Research Schedule [#y6a3002b]
***Step 1 (Finished) [#u6b962a1]
-Design and evaluation of a single Router
***Step 2 [#n84ecc4d] COLOR(blue){January 31, 2017} [#g69...
-Design of a 4x4 OASIS NoC (without PEs)
-Study the complexity, bandwidth, and Latency
***Step 3 COLOR(blue){February 28, 2017} [#g7a4a8a7]
-Investigate and study SIFT Algorithm
--''Reference'': [[SIFT Algorithm (in Japanese)>https://d...
***Step 4 COLOR(blue){April 30, 2017} [#z3d05ba1]
-Investigate SIFT Task Graph
-Investigate suitable PEs
-Investigate required hardware configuration
***Step 5 COLOR(blue){June 30, 2017} [#tdb0e927]
-Use Step 2 and integrate PEs, Memory, and NI.
***Step 5 COLOR(blue){September 30, 2017} [#e0b77ff3]
-Evaluate the performance of the system.
***Step 5 COLOR(blue){November 30, 2017} [#qc91854a]
-Debugging
***Step 5 COLOR(blue){December 15 - Janury 8, 2018} [#x65...
-Write MS thesis
*References [#ba027dbf]
-[[GT>Akihito Kajikawa]]
- Main references: Japanese spec: https://github.com/open...
-[[Small MIPS Processor in Verilog>https://drive.google.c...
-Other Links
--[[OASIS-VP GDoc Spec (editable)>https://docs.google.com...
--[[SIFT Lecture (Video)>https://www.youtube.com/watch?v=...
--[[SIFT Lecture (Japanese)>https://drive.google.com/file...
--[[SIFT Demo (Matlab)>https://drive.google.com/file/d/0B...
--[[Tapeout (by Akram)>https://drive.google.com/file/d/0B...
ページ名: