Ken Saito
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開始行:
CENTER:SIZE(40){COLOR(blue){Design and Analysis of Electr...
-[[Members-Internal]]
*Background (Problem Definition) [#x8959e48]
The huge computing power of many-core multi-processor sys...
Current [[PHENIC>http://aslweb.u-aizu.ac.jp/aslint/index....
*Research Goal [#t85a4382]
Hardware design and evaluation of Electrical Control Rout...
*Research Schedule [#k3603c5b]
***Step 0 (Mentor: D3 Achraf), COLOR(red){Completion Date...
-Take the Guidance Lectures: http://aslweb.u-aizu.ac.jp/a...
***Step 1 COLOR(red){Completion Date: %%July 30%%, August...
Read these references:
-[["Non-blocking Electro-optic Network-on-Chip Router for...
-[[Efficient Router Architecture, Design and Performance ...
***Step 2 COLOR(red){Completion Date: September 20, 2015....
Run these 2 tutorials on your machine:
-[[OASIS 3D Fault Tolerant Router Hardware Physical Desig...
-[[OASIS 3D Router Design Tutorial>http://web-ext.u-aizu....
***Step 3 COLOR(red){Due date: October 30, 2015.} [#pf0be...
CR Design
***Step 4 COLOR(red){Due date: November 30,2015.} [#jbcfc...
CR Evaluation
***Step 5 [#y00b6e77]
Thesis writing
*References[#jec7d6fe]
-[[????ʸ?ơ??? (Previous GT)>http://aslweb.u-aizu.ac.jp/a...
***Verilog Code [#g8eed850]
-[[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac....
終了行:
CENTER:SIZE(40){COLOR(blue){Design and Analysis of Electr...
-[[Members-Internal]]
*Background (Problem Definition) [#x8959e48]
The huge computing power of many-core multi-processor sys...
Current [[PHENIC>http://aslweb.u-aizu.ac.jp/aslint/index....
*Research Goal [#t85a4382]
Hardware design and evaluation of Electrical Control Rout...
*Research Schedule [#k3603c5b]
***Step 0 (Mentor: D3 Achraf), COLOR(red){Completion Date...
-Take the Guidance Lectures: http://aslweb.u-aizu.ac.jp/a...
***Step 1 COLOR(red){Completion Date: %%July 30%%, August...
Read these references:
-[["Non-blocking Electro-optic Network-on-Chip Router for...
-[[Efficient Router Architecture, Design and Performance ...
***Step 2 COLOR(red){Completion Date: September 20, 2015....
Run these 2 tutorials on your machine:
-[[OASIS 3D Fault Tolerant Router Hardware Physical Desig...
-[[OASIS 3D Router Design Tutorial>http://web-ext.u-aizu....
***Step 3 COLOR(red){Due date: October 30, 2015.} [#pf0be...
CR Design
***Step 4 COLOR(red){Due date: November 30,2015.} [#jbcfc...
CR Evaluation
***Step 5 [#y00b6e77]
Thesis writing
*References[#jec7d6fe]
-[[????ʸ?ơ??? (Previous GT)>http://aslweb.u-aizu.ac.jp/a...
***Verilog Code [#g8eed850]
-[[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac....
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