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開始行:
[[Michael Meyer]]
CENTER:SIZE(30){COLOR(blue){Fault-tolerant Photonic Mesh-...
*Schedule [#qd04e3be]
|Section|Completion Date|Draft|
|Abstract |July 22, 10 AM|[[Abstract.pdf]]|
|Introduction|July 27, 10 AM|[[Introduction>https://drive...
|Related Work|August 3, 6 PM|[[Related Work.pdf>https://d...
|System Architecture|August 10, 10 AM|[[System Architectu...
|Routing Algorithm|August 11, 10 AM|[[Routing Algorithm_v...
|Design Space Exploration|August 19, 10 AM|[[Design Space...
|Evaluation|August 31 %%August 27%%, 10 AM|[[Evaluation+v...
|Conclusion and Future Work|Sept 7, 10 AM|[[Conclusion an...
|Revision 2|Sept %%21%% 19, 10 AM|[[Revision 1>https://dr...
----
***0. Abstract [#v112563c]
- Summary of background info
- Summary of problem
- Summary of results
- Summary of benefits
***1. Introduction [#dae52410]
-Explain the problem which we have solved
-Explain why the problem is not already solved or other s...
-Explain why our solution is worth considering and why is...
-Write how the rest of the paper is structured
***2. Related work [#z107f75f]
- Briefly talk about Mesh
- Briefly Talk about Oasis
- Details about Photonic NoCs
- Details about Fault Tolerance
--Redundancy
--Rerouting
***3. System Implementation [#fd9fb312]
-3.1 Router Micro-architecture (FT Switch + Control)
-- You need to have FT routers with different ports(5, 4,...
-- Explanation of the selection of redundant MRs
Notes:
--Reduction of Crossing in your router means lower insert...
--Reduction of the number of MRRs in your router can offe...
-3.2 FT Routing Algorithm
***4. FT Router design Space Exploration [#w4f44e24]
-Investigate the Latency, area and optical power trade-of...
-COLOR(red){Analysis of Cross-talk}. Refer to the followi...
--Yiyuan Xie, Weihua Xu, Weilun Zhao, Yexiong Huang, Ting...
---Y. Xie, M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. ...
---M. Nikdast, J. Xu, X. Wu, Z. Wang, X. Wang, and Z. Wan...
---M. Nikdast, J. Xu, L. H. K. Duong, X. Wu, X. Wang, Z. ...
---M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang, Z....
-Analysis o Insertion Loss
***5. Evaluation [#u484357f]
-5.1 Methodology
-- How you evaluated your system
-- Performance metrics
-- Performance parameters
-5.2 Results
--A. Performance Evaluation
---Throughput
---ETE latency
--B. Complexity Evaluation
---Area (Erouter and ORouter)
---Total Power
---Total Energy
--C. Scalability and Reliability Evaluation
---Optical Signal to noise ratio (OSNR)
---Bit-Error-Rate
Ref. 1 [[Crosstalk noise and bit error rate analysis for ...
COLOR(red){Similar to Ref. 1, Develop your won Mathematic...
COLOR(red){IMPORTANT NOTES}
-1. For each of these three evaluations, compare with wel...
-2. Large and Realistic Benchmarks are needed
***5. Conclusions and Future Work [#t72a0ccf]
- Explain the problem which you have solved
- Explain your solution to the problem
- Explain why your solution is good: give some numbers
- Explain why the reader should be impressed by your work
- Give summary of results
- Give some future works
***References [#t0c66dfb]
- Use a .bib file from the start
-[1] L. P. Carloni, P. Pande, and Y. Xie, ??Networks-on-c...
interconnect paradigms: Advantages and challenges,?? in P...
the 2009 3rd ACM/IEEE International Symposium on Networks...
IEEE Computer Society, 2009, pp. 93–102.
-[2] F. N. Sibai, ??A two-dimensional low-diameter scalab...
for interconnecting thousands of cores,?? Parallel and Di...
IEEE Transactions on, vol. 23, no. 2, pp. 193–201, ...
-[3] A. B. Abdallah and M. Sowa, ??Basic Network-on-Chip ...
for Future Gigascale MCSoCs Applications: Communication a...
Orthogonalization,?? in JASSST2006, 2006.
-[4] A. Ben Ahmed, A. Ben Abdallah, and K. Kuroda, ??Arch...
design of ecient 3D network-on-chip (3D NoC) for custom ...
SoC,?? in Broadband, Wireless Computing, Communication an...
(BWCCA), 2010 International Conference on. IEEE, 2010, pp.
67–73.
-[5] G. Leary and K. S. Chatha, ??Design of noc for soc w...
use cases requiring guaranteed performance,?? in VLSI Des...
VLSID??10. 23rd International Conference on. IEEE, 2010, ...
205.
-[6] L. Benini and G. De Micheli, ??Networks on chips: a ...
Computer, vol. 35, no. 1, pp. 70–78, 2002.
-[7] ??ITRS Report Interconnect,?? http://www.itrs.net/IT...
20Mtgs,%20Presentations%20&%20Links/2011ITRS/2011Chapters/
2011Interconnect.pdf/, 2011, [Online; accessed 1-July-201...
-[8] J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Hor...
C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E...
et al., ??Three-dimensional silicon integration,?? IBM Jo...
and Development, vol. 52, no. 6, pp. 553–569, 2008.
-[9] S. Fujita, K. Nomura, K. Abe, and T. H. Lee, ??3d on...
technology based on post-silicon devices for future netwo...
in 2006 1st International Conference on Nano-Networks and...
2006.
-[10] Y.-L. Jeang, T.-s. Wey, H.-Y. Wang, and C.-W. Hung,...
for network-on-chip design,?? in Innovative Computing, In...
and Control, 2007. ICICIC??07. Second International Confe...
on. IEEE, 2007, pp. 262–262.
-[11] ??Replacing Silicon with Carbon Nanotubes: Why its ...
http://www.eeweb.com/blog/aaronfranklin, 2012, [Online; a...
1-April-2015].
-[12] J. Wolfe, ?? Why IBM and Intel Are Chasing the 100B...
in Nanophotonics,?? 2012, online; accessed 1-July-2015. [...
Available: nurlfhttp://www.forbes.com/sites/joshwolfe/201...
why-ibm-and-intel-are-chasing-the-100b-opportunity-in-nan...
g
-[13] D. Vantrease, R. Schreiber, M. Monchiero, M. McLare...
M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, an...
??Corona: System implications of emerging nanophotonic te...
in ACM SIGARCH Computer Architecture News, vol. 36, no. 3...
Computer Society, 2008, pp. 153–164.
-[14] R. Kumar, V. Zyuban, and D. M. Tullsen, ??Interconn...
architectures: Understanding mechanisms, overheads and sc...
Computer Architecture, 2005. ISCA??05. Proceedings. 32nd ...
Symposium on. IEEE, 2005, pp. 408–419.
-[15] R. Kappeler, ??Radiation testing of micro photonic ...
Project Report. ESA/ESTEC. September 29, 2004. Ref. No.: ...
-[16] Y. Yang, ??Issues of esd protection in nano-scale c...
George Mason University, 2010.
-[17] J. Keane and C. H. Kim, ??An odomoeter for cpus,?? ...
vol. 48, no. 5, pp. 28–33, 2011.
-[18] S. Luryi, J. Xu, and A. Zaslavsky, Future trends in...
the nano creek. John Wiley & Sons, 2007.
-[19] Z.-S. Hu, F.-Y. Hung, K.-J. Chen, S.-J. Chang, W.-K...
Y. Liao, ??Improvement in thermal degradation of zno phot...
by embedding silver oxide nanoparticles,?? Functional Mat...
vol. 6, no. 01, p. 1350001, 2013.
-[20] Z. Tu, Z. Zhou, and X. Wang, ??Reliability consider...
germanium waveguide photodetectors,?? in SPIE OPTO. Inter...
Society for Optics and Photonics, 2014, pp. 89 820W–...
-[21] M. Agarwal, B. C. Paul, M. Zhang, and S. Mitra, ??C...
and its application to transistor aging,?? in VLSI Test S...
2007. 25th IEEE. IEEE, 2007, pp. 277–286.
-[22] J. Keane, T.-H. Kim, and C. H. Kim, ??An on-chip nb...
pmos threshold voltage degradation,?? Very Large Scale In...
(VLSI) Systems, IEEE Transactions on, vol. 18, no. 6, pp....
2010.
-[23] E. Mintarno, J. Skaf, R. Zheng, J. B. Velamala, Y. ...
R. W. Dutton, and S. Mitra, ??Self-tuning for maximized l...
ciency in the presence of circuit aging,?? Computer-Aide...
Integrated Circuits and Systems, IEEE Transactions on, vo...
pp. 760–773, 2011.
-[24] M. Radetzki, C. Feng, X. Zhao, and A. Jantsch, ??Me...
in networks-on-chip,?? ACM Computing Surveys (CSUR), vol....
no. 1, p. 8, 2013.
-[25] K. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshw...
S. Sivakumar, G. Taylor, P. VanDerVoorn, and K. Zawadzki,...
process variation in intel??s 45nm cmos technology.?? Int...
Journal, vol. 12, no. 2, 2008.
-[26] S. K. Saha, ??Modeling process variability in scale...
IEEE Design & Test of Computers, no. 2, pp. 8–16, 2...
-[27] S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M...
K. Tiensyrj??a, and A. Hemani, ??A network on chip archit...
methodology,?? in VLSI, 2002. Proceedings. IEEE Computer ...
Annual Symposium on. IEEE, 2002, pp. 105–112.
-[28] M. Mohamed, ??Silicon nanophotonics for many-core o...
Ph.D. dissertation, University of Colorado, 2013.
-[29] A. B. Ahmed and A. B. Abdallah, ??Architecture and ...
low-latency, and fault-tolerant routing algorithm for 3Dn...
on-chip (3D-NoC),?? The Journal of Supercomputing, vol. 66,
no. 3, pp. 1507–1532, 2013.
-[30] Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A...
??Firefly: illuminating future network-on-chip with nanop...
ACM SIGARCH Computer Architecture News, vol. 37, no. 3. A...
2009, pp. 429–440.
-[31] A. Ben Ahmed and A. Ben Abdallah, ??Graceful deadlo...
fault-tolerant routing algorithm for 3D Network-on-Chip a...
Journal of Parallel and Distributed Computing, vol. 74, n...
pp. 2229–2240, 2014. [Online]. Available: http://we...
benab/publications/journals/JPDC14/JPDC-preprint.pdf
-[32] A. B. Abdallah, Multicore Systems On-chip: Practical
Software/hardware Design. Springer, 2013, vol. 2.
-[33] A. B. Abdallah, M. Nakamura, A. B. Ahmed, M. Meyer,...
Y. Okuyama, ??Fault-tolerant router for highly-reliable m...
systems.??
-[34] A. Shacham, K. Bergman, and L. P. Carloni, ??Photon...
for future generations of chip multiprocessors,?? Compute...
Transactions on, vol. 57, no. 9, pp. 1246–1260, 2008.
-[35] G. Ramesh and S. SundaraVadivelu, ??A reliable and ...
for optical wdm networks,?? arXiv preprint arXiv:0912.060...
-[36] P. K. Loh and W.-J. Hsu, ??Design of a viable fault...
strategy for optical-based grids,?? in Parallel and Distr...
and Applications. Springer, 2003, pp. 112–126.
-[37] Q. Xingyun, F. Quanyou, C. Yongran, D. Qiang, and D...
tolerant bu erless optical interconnection network,?? in ...
Information Science, 2009. ICIS 2009. Eighth IEEE/ACIS In...
Conference on. IEEE, 2009, pp. 249–254.
-[38]D. Xiang, Y. Zhang, S. Shan, and Y. Xu, ??A fault-to...
algorithm design for on-chip optical networks,?? in Relia...
Systems (SRDS), 2013 IEEE 32nd International Symposium on...
2013, pp. 1–9.
-[39] M. McLaren, N. L. Binkert, A. L. Davis, and M. Flor...
cient and fault-tolerant resonator-based modulation and ...
division multiplexing systems,?? Apr. 22 2014, uS Patent ...
-[40] L. Sahasrabuddhe, S. Ramamurthy, and B. Mukherjee, ...
in ip-over-wdm networks: Wdm protection versus ip restora...
Selected Areas in Communications, IEEE Journal on, vol. 2...
21–33, 2002.
-[41] J. Zhang and B. Mukheriee, ??A review of fault mana...
mesh networks: basic concepts and research challenges,?? ...
vol. 18, no. 2, pp. 41–48, 2004.
-[42] B. Ahmed and A. B. Abdallah, ??PHENIC: Towards Phot...
on-Chip Architecture for High-throughput Many-core System...
Chip,?? in IEEE Proc. of the 14th Int. Conf. on Sciences ...
Techniques of Automatic Control and Computer Eng, 2013.
-[43] A. K. Todimala, Fault-tolerance using shared path p...
division multiplexing optical transport networks. Univers...
Nebraska at Lincoln, 2006.
-[44] M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang,...
and Z. Wang, ??Systematic analysis of crosstalk noise in ...
optical networks-on-chip,?? Computer-Aided Design of Inte...
Circuits and Systems, IEEE Transactions on, vol. 33, no. ...
2014.
-[45] R. Kumar, D. M. Tullsen, and N. P. Jouppi, ??Core a...
for heterogeneous chip multiprocessors,?? in Proceedings ...
15th international conference on Parallel architectures a...
techniques. ACM, 2006, pp. 23–32.
-[46] M. J. Cianchetti, J. C. Kerekes, and D. H. Albonesi...
rapid transit optical routing network,?? in ACM SIGARCH C...
Architecture News, vol. 37, no. 3. ACM, 2009, pp. 441R...
終了行:
[[Michael Meyer]]
CENTER:SIZE(30){COLOR(blue){Fault-tolerant Photonic Mesh-...
*Schedule [#qd04e3be]
|Section|Completion Date|Draft|
|Abstract |July 22, 10 AM|[[Abstract.pdf]]|
|Introduction|July 27, 10 AM|[[Introduction>https://drive...
|Related Work|August 3, 6 PM|[[Related Work.pdf>https://d...
|System Architecture|August 10, 10 AM|[[System Architectu...
|Routing Algorithm|August 11, 10 AM|[[Routing Algorithm_v...
|Design Space Exploration|August 19, 10 AM|[[Design Space...
|Evaluation|August 31 %%August 27%%, 10 AM|[[Evaluation+v...
|Conclusion and Future Work|Sept 7, 10 AM|[[Conclusion an...
|Revision 2|Sept %%21%% 19, 10 AM|[[Revision 1>https://dr...
----
***0. Abstract [#v112563c]
- Summary of background info
- Summary of problem
- Summary of results
- Summary of benefits
***1. Introduction [#dae52410]
-Explain the problem which we have solved
-Explain why the problem is not already solved or other s...
-Explain why our solution is worth considering and why is...
-Write how the rest of the paper is structured
***2. Related work [#z107f75f]
- Briefly talk about Mesh
- Briefly Talk about Oasis
- Details about Photonic NoCs
- Details about Fault Tolerance
--Redundancy
--Rerouting
***3. System Implementation [#fd9fb312]
-3.1 Router Micro-architecture (FT Switch + Control)
-- You need to have FT routers with different ports(5, 4,...
-- Explanation of the selection of redundant MRs
Notes:
--Reduction of Crossing in your router means lower insert...
--Reduction of the number of MRRs in your router can offe...
-3.2 FT Routing Algorithm
***4. FT Router design Space Exploration [#w4f44e24]
-Investigate the Latency, area and optical power trade-of...
-COLOR(red){Analysis of Cross-talk}. Refer to the followi...
--Yiyuan Xie, Weihua Xu, Weilun Zhao, Yexiong Huang, Ting...
---Y. Xie, M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. ...
---M. Nikdast, J. Xu, X. Wu, Z. Wang, X. Wang, and Z. Wan...
---M. Nikdast, J. Xu, L. H. K. Duong, X. Wu, X. Wang, Z. ...
---M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang, Z....
-Analysis o Insertion Loss
***5. Evaluation [#u484357f]
-5.1 Methodology
-- How you evaluated your system
-- Performance metrics
-- Performance parameters
-5.2 Results
--A. Performance Evaluation
---Throughput
---ETE latency
--B. Complexity Evaluation
---Area (Erouter and ORouter)
---Total Power
---Total Energy
--C. Scalability and Reliability Evaluation
---Optical Signal to noise ratio (OSNR)
---Bit-Error-Rate
Ref. 1 [[Crosstalk noise and bit error rate analysis for ...
COLOR(red){Similar to Ref. 1, Develop your won Mathematic...
COLOR(red){IMPORTANT NOTES}
-1. For each of these three evaluations, compare with wel...
-2. Large and Realistic Benchmarks are needed
***5. Conclusions and Future Work [#t72a0ccf]
- Explain the problem which you have solved
- Explain your solution to the problem
- Explain why your solution is good: give some numbers
- Explain why the reader should be impressed by your work
- Give summary of results
- Give some future works
***References [#t0c66dfb]
- Use a .bib file from the start
-[1] L. P. Carloni, P. Pande, and Y. Xie, ??Networks-on-c...
interconnect paradigms: Advantages and challenges,?? in P...
the 2009 3rd ACM/IEEE International Symposium on Networks...
IEEE Computer Society, 2009, pp. 93–102.
-[2] F. N. Sibai, ??A two-dimensional low-diameter scalab...
for interconnecting thousands of cores,?? Parallel and Di...
IEEE Transactions on, vol. 23, no. 2, pp. 193–201, ...
-[3] A. B. Abdallah and M. Sowa, ??Basic Network-on-Chip ...
for Future Gigascale MCSoCs Applications: Communication a...
Orthogonalization,?? in JASSST2006, 2006.
-[4] A. Ben Ahmed, A. Ben Abdallah, and K. Kuroda, ??Arch...
design of ecient 3D network-on-chip (3D NoC) for custom ...
SoC,?? in Broadband, Wireless Computing, Communication an...
(BWCCA), 2010 International Conference on. IEEE, 2010, pp.
67–73.
-[5] G. Leary and K. S. Chatha, ??Design of noc for soc w...
use cases requiring guaranteed performance,?? in VLSI Des...
VLSID??10. 23rd International Conference on. IEEE, 2010, ...
205.
-[6] L. Benini and G. De Micheli, ??Networks on chips: a ...
Computer, vol. 35, no. 1, pp. 70–78, 2002.
-[7] ??ITRS Report Interconnect,?? http://www.itrs.net/IT...
20Mtgs,%20Presentations%20&%20Links/2011ITRS/2011Chapters/
2011Interconnect.pdf/, 2011, [Online; accessed 1-July-201...
-[8] J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Hor...
C. S. Patel, R. J. Polastre, K. Sakuma, R. Sirdeshmukh, E...
et al., ??Three-dimensional silicon integration,?? IBM Jo...
and Development, vol. 52, no. 6, pp. 553–569, 2008.
-[9] S. Fujita, K. Nomura, K. Abe, and T. H. Lee, ??3d on...
technology based on post-silicon devices for future netwo...
in 2006 1st International Conference on Nano-Networks and...
2006.
-[10] Y.-L. Jeang, T.-s. Wey, H.-Y. Wang, and C.-W. Hung,...
for network-on-chip design,?? in Innovative Computing, In...
and Control, 2007. ICICIC??07. Second International Confe...
on. IEEE, 2007, pp. 262–262.
-[11] ??Replacing Silicon with Carbon Nanotubes: Why its ...
http://www.eeweb.com/blog/aaronfranklin, 2012, [Online; a...
1-April-2015].
-[12] J. Wolfe, ?? Why IBM and Intel Are Chasing the 100B...
in Nanophotonics,?? 2012, online; accessed 1-July-2015. [...
Available: nurlfhttp://www.forbes.com/sites/joshwolfe/201...
why-ibm-and-intel-are-chasing-the-100b-opportunity-in-nan...
g
-[13] D. Vantrease, R. Schreiber, M. Monchiero, M. McLare...
M. Fiorentino, A. Davis, N. Binkert, R. G. Beausoleil, an...
??Corona: System implications of emerging nanophotonic te...
in ACM SIGARCH Computer Architecture News, vol. 36, no. 3...
Computer Society, 2008, pp. 153–164.
-[14] R. Kumar, V. Zyuban, and D. M. Tullsen, ??Interconn...
architectures: Understanding mechanisms, overheads and sc...
Computer Architecture, 2005. ISCA??05. Proceedings. 32nd ...
Symposium on. IEEE, 2005, pp. 408–419.
-[15] R. Kappeler, ??Radiation testing of micro photonic ...
Project Report. ESA/ESTEC. September 29, 2004. Ref. No.: ...
-[16] Y. Yang, ??Issues of esd protection in nano-scale c...
George Mason University, 2010.
-[17] J. Keane and C. H. Kim, ??An odomoeter for cpus,?? ...
vol. 48, no. 5, pp. 28–33, 2011.
-[18] S. Luryi, J. Xu, and A. Zaslavsky, Future trends in...
the nano creek. John Wiley & Sons, 2007.
-[19] Z.-S. Hu, F.-Y. Hung, K.-J. Chen, S.-J. Chang, W.-K...
Y. Liao, ??Improvement in thermal degradation of zno phot...
by embedding silver oxide nanoparticles,?? Functional Mat...
vol. 6, no. 01, p. 1350001, 2013.
-[20] Z. Tu, Z. Zhou, and X. Wang, ??Reliability consider...
germanium waveguide photodetectors,?? in SPIE OPTO. Inter...
Society for Optics and Photonics, 2014, pp. 89 820W–...
-[21] M. Agarwal, B. C. Paul, M. Zhang, and S. Mitra, ??C...
and its application to transistor aging,?? in VLSI Test S...
2007. 25th IEEE. IEEE, 2007, pp. 277–286.
-[22] J. Keane, T.-H. Kim, and C. H. Kim, ??An on-chip nb...
pmos threshold voltage degradation,?? Very Large Scale In...
(VLSI) Systems, IEEE Transactions on, vol. 18, no. 6, pp....
2010.
-[23] E. Mintarno, J. Skaf, R. Zheng, J. B. Velamala, Y. ...
R. W. Dutton, and S. Mitra, ??Self-tuning for maximized l...
ciency in the presence of circuit aging,?? Computer-Aide...
Integrated Circuits and Systems, IEEE Transactions on, vo...
pp. 760–773, 2011.
-[24] M. Radetzki, C. Feng, X. Zhao, and A. Jantsch, ??Me...
in networks-on-chip,?? ACM Computing Surveys (CSUR), vol....
no. 1, p. 8, 2013.
-[25] K. Kuhn, C. Kenyon, A. Kornfeld, M. Liu, A. Maheshw...
S. Sivakumar, G. Taylor, P. VanDerVoorn, and K. Zawadzki,...
process variation in intel??s 45nm cmos technology.?? Int...
Journal, vol. 12, no. 2, 2008.
-[26] S. K. Saha, ??Modeling process variability in scale...
IEEE Design & Test of Computers, no. 2, pp. 8–16, 2...
-[27] S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M...
K. Tiensyrj??a, and A. Hemani, ??A network on chip archit...
methodology,?? in VLSI, 2002. Proceedings. IEEE Computer ...
Annual Symposium on. IEEE, 2002, pp. 105–112.
-[28] M. Mohamed, ??Silicon nanophotonics for many-core o...
Ph.D. dissertation, University of Colorado, 2013.
-[29] A. B. Ahmed and A. B. Abdallah, ??Architecture and ...
low-latency, and fault-tolerant routing algorithm for 3Dn...
on-chip (3D-NoC),?? The Journal of Supercomputing, vol. 66,
no. 3, pp. 1507–1532, 2013.
-[30] Y. Pan, P. Kumar, J. Kim, G. Memik, Y. Zhang, and A...
??Firefly: illuminating future network-on-chip with nanop...
ACM SIGARCH Computer Architecture News, vol. 37, no. 3. A...
2009, pp. 429–440.
-[31] A. Ben Ahmed and A. Ben Abdallah, ??Graceful deadlo...
fault-tolerant routing algorithm for 3D Network-on-Chip a...
Journal of Parallel and Distributed Computing, vol. 74, n...
pp. 2229–2240, 2014. [Online]. Available: http://we...
benab/publications/journals/JPDC14/JPDC-preprint.pdf
-[32] A. B. Abdallah, Multicore Systems On-chip: Practical
Software/hardware Design. Springer, 2013, vol. 2.
-[33] A. B. Abdallah, M. Nakamura, A. B. Ahmed, M. Meyer,...
Y. Okuyama, ??Fault-tolerant router for highly-reliable m...
systems.??
-[34] A. Shacham, K. Bergman, and L. P. Carloni, ??Photon...
for future generations of chip multiprocessors,?? Compute...
Transactions on, vol. 57, no. 9, pp. 1246–1260, 2008.
-[35] G. Ramesh and S. SundaraVadivelu, ??A reliable and ...
for optical wdm networks,?? arXiv preprint arXiv:0912.060...
-[36] P. K. Loh and W.-J. Hsu, ??Design of a viable fault...
strategy for optical-based grids,?? in Parallel and Distr...
and Applications. Springer, 2003, pp. 112–126.
-[37] Q. Xingyun, F. Quanyou, C. Yongran, D. Qiang, and D...
tolerant bu erless optical interconnection network,?? in ...
Information Science, 2009. ICIS 2009. Eighth IEEE/ACIS In...
Conference on. IEEE, 2009, pp. 249–254.
-[38]D. Xiang, Y. Zhang, S. Shan, and Y. Xu, ??A fault-to...
algorithm design for on-chip optical networks,?? in Relia...
Systems (SRDS), 2013 IEEE 32nd International Symposium on...
2013, pp. 1–9.
-[39] M. McLaren, N. L. Binkert, A. L. Davis, and M. Flor...
cient and fault-tolerant resonator-based modulation and ...
division multiplexing systems,?? Apr. 22 2014, uS Patent ...
-[40] L. Sahasrabuddhe, S. Ramamurthy, and B. Mukherjee, ...
in ip-over-wdm networks: Wdm protection versus ip restora...
Selected Areas in Communications, IEEE Journal on, vol. 2...
21–33, 2002.
-[41] J. Zhang and B. Mukheriee, ??A review of fault mana...
mesh networks: basic concepts and research challenges,?? ...
vol. 18, no. 2, pp. 41–48, 2004.
-[42] B. Ahmed and A. B. Abdallah, ??PHENIC: Towards Phot...
on-Chip Architecture for High-throughput Many-core System...
Chip,?? in IEEE Proc. of the 14th Int. Conf. on Sciences ...
Techniques of Automatic Control and Computer Eng, 2013.
-[43] A. K. Todimala, Fault-tolerance using shared path p...
division multiplexing optical transport networks. Univers...
Nebraska at Lincoln, 2006.
-[44] M. Nikdast, J. Xu, X. Wu, W. Zhang, Y. Ye, X. Wang,...
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