Hiroki Tanaka
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開始行:
[Members-Internal]]
CENTER:SIZE(40){COLOR(#990199){Physical Design of 3D OASI...
CENTER:&ref(pipeline.jpg,,10%);
CENTER:COLOR(green){3D-OASIS-NoC system architecture}
**Background [#nec7d6fe]
During this last decade, 3D- Network-on-Chips (3D-NoCs) h...
One of the major issues in 3D-NoC systems is how to verif...
Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D...
However, logic modules were connected to routers instead ...
**Research goal[#mec7d6fe]
The main goals of this research are:
-1. Study OASIS 3D Router Architecture
-2. Design the Physical router using Design Compiler (for...
-3. Verify the correctness at each step using ModelSim
-4. Evaluate the performance of the final system (Area, p...
-5. Write a thesis
**Research plan[#lec7d6fe]
** Prerequisite [#l901bf10]
//- Verilog-HDL
//- Altera Quartus II
//- Altera ModelSim
//- Synopsis Design Compiler
//- Cadence SoC Encounter
**References[#jec7d6fe]
-[[K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ''Advanc...
- [[Guidance Lectures]]
- [[3D-ONoC-Verilog]]
- A. Ben Ahmed, On the Design of a 3D Network-on-Chip for...
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/thes...
- R. Okada, A. Ben Abdallah,Architecture and Design of Co...
** Benchmark suite [#c4629d5d]
-JPEG
-Matrix multiplication
-Transpose traffic pattern
-Uniform traffic pattern
--[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/benchm...
--[[ppt>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/benchm...
終了行:
[Members-Internal]]
CENTER:SIZE(40){COLOR(#990199){Physical Design of 3D OASI...
CENTER:&ref(pipeline.jpg,,10%);
CENTER:COLOR(green){3D-OASIS-NoC system architecture}
**Background [#nec7d6fe]
During this last decade, 3D- Network-on-Chips (3D-NoCs) h...
One of the major issues in 3D-NoC systems is how to verif...
Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D...
However, logic modules were connected to routers instead ...
**Research goal[#mec7d6fe]
The main goals of this research are:
-1. Study OASIS 3D Router Architecture
-2. Design the Physical router using Design Compiler (for...
-3. Verify the correctness at each step using ModelSim
-4. Evaluate the performance of the final system (Area, p...
-5. Write a thesis
**Research plan[#lec7d6fe]
** Prerequisite [#l901bf10]
//- Verilog-HDL
//- Altera Quartus II
//- Altera ModelSim
//- Synopsis Design Compiler
//- Cadence SoC Encounter
**References[#jec7d6fe]
-[[K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ''Advanc...
- [[Guidance Lectures]]
- [[3D-ONoC-Verilog]]
- A. Ben Ahmed, On the Design of a 3D Network-on-Chip for...
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/thes...
- R. Okada, A. Ben Abdallah,Architecture and Design of Co...
** Benchmark suite [#c4629d5d]
-JPEG
-Matrix multiplication
-Transpose traffic pattern
-Uniform traffic pattern
--[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/benchm...
--[[ppt>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/benchm...
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