Eiji Yamashita
をテンプレートにして作成
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開始行:
[[Members-Internal]]
CENTER:SIZE(50){COLOR(green){Design and Evaluation of a S...
*Research Bakground [#v2d18f30]
TBC
*Research Goal [#i33b5e55]
-Design in hardware (Verilog, Cedence or/and Vivado Desig...
-Evalaute the hardware compelxity: Power, Area
-Run an Image Recogntion Benchmark/DS to verify the design
Research Scehdule
- Study previous GT thesis - LIF (Leaky Integrate and Fir...
--https://adaptive.u-aizu.ac.jp/aslint/index.php?Theses#x...
--Make a presentaiotn on June 3, 2019, Time: 5 PM
*References [#g3d35207]
-[[LIF Neron>https://drive.google.com/file/d/0B2HMlO4p7Su...
-[[Crossbar>https://drive.google.com/file/d/0B2HMlO4p7Suw...
-[[SNPC Specification>https://drive.google.com/file/d/0B2...
-[[STDP>https://drive.google.com/file/d/0B2HMlO4p7SuwZV9V...
-[[Simple LIF Neuron in Verilog>https://drive.google.com/...
終了行:
[[Members-Internal]]
CENTER:SIZE(50){COLOR(green){Design and Evaluation of a S...
*Research Bakground [#v2d18f30]
TBC
*Research Goal [#i33b5e55]
-Design in hardware (Verilog, Cedence or/and Vivado Desig...
-Evalaute the hardware compelxity: Power, Area
-Run an Image Recogntion Benchmark/DS to verify the design
Research Scehdule
- Study previous GT thesis - LIF (Leaky Integrate and Fir...
--https://adaptive.u-aizu.ac.jp/aslint/index.php?Theses#x...
--Make a presentaiotn on June 3, 2019, Time: 5 PM
*References [#g3d35207]
-[[LIF Neron>https://drive.google.com/file/d/0B2HMlO4p7Su...
-[[Crossbar>https://drive.google.com/file/d/0B2HMlO4p7Suw...
-[[SNPC Specification>https://drive.google.com/file/d/0B2...
-[[STDP>https://drive.google.com/file/d/0B2HMlO4p7SuwZV9V...
-[[Simple LIF Neuron in Verilog>https://drive.google.com/...
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