Hiroki Tanaka の編集

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CENTER:SIZE(40){COLOR(#990199){Physical Design of 3D OASIS Router }}
CENTER:&ref(pipeline.jpg,,10%);
CENTER:COLOR(green){3D-OASIS-NoC system architecture}

**Background [#nec7d6fe]

During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.

One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research include a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations. Therefore, prototyping is an essential design phase for evaluating the performance of NoC architecture under real applications.

Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [[[1>http://aslweb.u-aizu.ac.jp/aslwiki/index.php?Hiroki%20Tanaka#c4629d5d]]].
However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.

**Research goal[#mec7d6fe]

The main goals of this research are:

-1. Study OASIS 3D Router Architecture

-2. Design the Physical router using Design Compiler (for Synthesis) and SoC Enounter (for Place and route)

-3. Verify the correctness at each step using ModelSim

-4. Evaluate the performance of the final system (Area, power, latency, ...).

-5. Write a thesis

**Research plan[#lec7d6fe]

** Prerequisite [#l901bf10]
//- Verilog-HDL
//- Altera Quartus II
//- Altera ModelSim
//- Synopsis Design Compiler
//- Cadence SoC Encounter

**References[#jec7d6fe]

-[[K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ''Advanced Design Issues for OASIS Network-on-Chip Architecture'',IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Mori.pdf]]

- [[Guidance Lectures]]

- [[3D-ONoC-Verilog]]

- A. Ben Ahmed, On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu.
[[Thesis>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], [[slides>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]]

- R. Okada, A. Ben Abdallah,Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC [[Thesis>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011.pdf]], [[slides>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Okada-BS-11/s1160048_GT2011-slides.pdf]], [[Technical Report>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/RyuyaOkada-TR2011.pdf]], [[Webpage>Ryuya Okada]]

** Benchmark suite [#c4629d5d]
-JPEG
-Matrix multiplication
-Transpose traffic pattern
-Uniform traffic pattern
--[[PDF>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/benchmarks.pdf]] 
--[[ppt>http://aslweb.u-aizu.ac.jp/~m5141153/tasks/benchmarks.ppt]]

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