Eiji Yamashita の編集

[[Members-Internal]]

CENTER:SIZE(50){COLOR(green){Design and Evaluation of a Spiking Neuron Processing Core (SNPC) for Adaptive Neuropromorhic System}}

*Research Bakground [#v2d18f30]

TBC

*Research Goal [#i33b5e55]

-Design in hardware (Verilog, Cedence or/and Vivado Design Suite - Xilinx) a 64x64 Spiking Neuron Core (SNPC) based on crossbar and STDP (Spike-Timing-Dependent-Plasticity).
-Evalaute the hardware compelxity: Power, Area 
-Run an Image Recogntion Benchmark/DS to verify the design

Research Scehdule

- Study previous GT thesis - LIF (Leaky Integrate and Fire) core

--https://adaptive.u-aizu.ac.jp/aslint/index.php?Theses#x191b349

--Make a presentaiotn on June 3, 2019, Time: 5 PM

*References [#g3d35207]

-[[LIF Neron>https://drive.google.com/file/d/0B2HMlO4p7SuwMEtPN1lJY3loZ0hsc1lvTWdaLTFJdlR1djdV/view?usp=sharing]]

-[[Crossbar>https://drive.google.com/file/d/0B2HMlO4p7SuwSUpmNzRfN1NMVlZkZjZIWFQ1T2RCd2YwbE9v/view?usp=sharing]]

-[[SNPC Specification>https://drive.google.com/file/d/0B2HMlO4p7SuwWm4wWlVqZ0c5Q1dlSE1jREd3ZGUxOXVXUTVN/view?usp=sharing]]

-[[STDP>https://drive.google.com/file/d/0B2HMlO4p7SuwZV9VM3BCQVlEZTZkTHQtcTNjTUF6aHFPaFdZ/view?usp=sharing]]

-[[Simple LIF Neuron in Verilog>https://drive.google.com/drive/folders/1vrKp6e_SlpVLZCXpXjd8W0gCg-j7vBF7?usp=sharing]] (Developed and designed with Quartus II by Kanta Suzuki, BS 2017)

タイムスタンプを変更しない