Altera CAD Tutorial の編集

*Designing with Quartus II, SOPC and DE2 - All you need to know! [#u135fe6a]

#contents
**Introduction to Verilog HDL [#h4cfd520]
Before you use Quartus II and other CAD tools, you need first to understand how to program with Verilog HDL. To do so, read this tutorial about  
[[Verilog HDL>http://www.u-aizu.ac.jp/%7Ebenab/classes/ca/2008/doc/verilog_tutorial_v2.pdf]].

**Quartus II [#y73f4c92]
-Target Device
#ref(DE2_70.jpg,,50%,DE2)
-The desired desing
#ref(Quartus_light_system_1.png,,50%,)
#ref(Quartus_light_system_table.png,,50%,)
**1 Starting a New Project [#ye9cebd4]
+Activation of Quartus 2
#ref(Quartus_Quartus_0.png,,50%,)
+Select File->New Project Wizard
+New Project Wizard window appears
#ref(Quartus_New_Project_Wiz_Intro.png,,50%,)
+Click Next
+Select introtutorial as a working directory
+Type light as a project name
+Automatily "light" appears as a top-level design entity
#ref(Quartus_New_Project_Wiz_Dir.png,,50%,)
+Click Next
#ref(Quartus_New_Project_Wiz_Add.png,,50%,)
+Click Next
+Select Cyclone 2 as a Family in Device family area
+Select EP2C35F672C6 as a target device name in Available devices area
#ref(Quartus_New_Project_Wiz_Fam.png,,50%,)
+Click Next
#ref(Quartus_New_Project_Wiz_EDA.png,,50%,)
+Click Next
#ref(Quartus_New_Project_Wiz_Sum.png,,50%,)
+Click Finish
#ref(Quartus_Quartus_light_0.png,,50%,)

**2 Design Entry Using Verilog Code [#k41b74f1]
+Select File->New
+Choose Design Files->Verilog HDL File
#ref(Quartus_New_Verilg_HDL.png,,50%,)
+Click OK
#ref(Quartus_light_0.png,,50%,)
+Make a program
#ref(Quartus_light_1.png,,50%,)
+Select File->Save As
+Name "light"
+Choose Verilog VHL File as file type
#ref(Quartus_light_save.png,,50%,)
+Click OK
#ref(Quartus_light_2.png,,50%,)

**3 Compiling the Designed Circuit [#q469f5e4]
+Select Processing->Start compilation
#ref(Quartus_Compilation.png,,50%,)
+Click OK
#ref(Quartus_light_3.png,,50%,)

**4 Pin Assignment [#o9473ab9]
+Select Assignments->Pins
//#ref(Quartus_Pin_Planner_0,,50%,)
+Double Click a empty space on Location and f
+Scroll down and select PIN_AE22
+Double Click a empty space on Location and x1
+Scroll down and select PIN_N26
+Double Click a empty space on Location and x2
+Scroll down and select PIN_N25
#ref(Quartus_Pin_Planner_1.png,,50%,)
+Select File->Close
#ref(Quartus_light_4.png,,50%,)

**5.Simulation the Designed Circuit [#r54b626f]
***5-1.Design Wave Form [#lede14d1]
+Select File->New
+Choose Design Verification/Debugging->Vector Waveform File
#ref(Quartus_New_Vector_Waveform.png,,50%,)
+Click OK
#ref(Quartus_light_5.png,,50%,)
+Select Edit->End Time
+Enter 200 and select ns
#ref(Quartus_End_Time.png,,50%,)
+Click OK
#ref(Quartus_light_8.png,,50%,)
+Select View->Fit in Window
#ref(Quartus_light_9.png,,50%,)
+Select Edit->Insert->Insert Node or Bus
#ref(Quartus_Insert_Node_or_Bus_0.png,,50%,)
+Click Node Finder
+Pull down and select Pin:all in Filter area
+Click >> 
#ref(Quartus_Node_Finder_0.png,,50%,)
+Click OK
#ref(Quartus_Insert_Node_or_Bus_1.png,,50%,)
+Click OK
#ref(Quartus_light_10.png,,50%,)
+Set x1 to 0 in the time interval 0 to 100ns
+Set x1 to 1 in the time interval 100 to 200 ns
+Set x2 to 0 in the time interval 0 to 50 ns and 100 to 150 ns
+Set x2 to 1 in the time interval 50 to 100 ns and 150 to 200 ns
#ref(Quartus_light_11.png,,50%,)
+Select File->Save As (file name is light.vwf)
#ref(Quartus_light_vwf_save.png,,50%,)
+Click OK
#ref(Quartus_light_12.png,,50%,)

***5-2.Performance the Simulation -Functional Simulation [#s3dcda44]
+Select Assignments->Settings
+Select Simulator Settings on Category tree
+Choose Functional as the Simulation mode
+Choose light.vwf file as the Simulation input
#ref(Quartus_Settings_Simulator.png,,50%,)
+Click OK
#ref(Quartus_light_13.png,,50%,)
+Select Processing->Generate Functional Simulation Netlist
#ref(Quartus_Netlist_Generation.png,,50%,)
+Select OK
#ref(Quartus_light_14.png,,50%,)
+Select Processing->Start Simulation 
#ref(Quartus_Simulator.png,,50%,)
+Click OK
#ref(Quartus_light_15.png,,50%,)
+Select View->Fit in Window
#ref(Quartus_light_16.png,,50%,)

***5-3.Performance the Simulation -Timing Simulation [#u02a09a1]
+Select Assignments->Settings
+Select Simulator Settings on Category tree
+Choose Timing as the simulation mode
#ref(Quartus_Settings_Simulator_2.png,,50%,)
+Click OK
#ref(Quartus_light_17.png,,50%,)
+Select Processing->Start Simulation
#ref(Quartus_Simulator_2.png,,50%,)
+Click OK
#ref(Quartus_light_18.png,,50%,)

**6.Programming and Configuring the FPGA Device [#oc67e12b]
-&color(red,){Before you download configuration data to the board, you must install the USB-Blaster driver};
-[[Getting Started with Altera's DE2 Board>ftp://ftp.altera.com/up/pub/Tutorials/DE2/Digital_Logic/tut_initialDE2.pdf]] for information about installing the driver
***6-1.JTAG Programming (Hardware) [#ed12202a]
+Connect a host computer and the DE2 board
+Power on the DE2 board
***6-2.JTAG Programming (Software) [#cf89fd64]
+Flip the RUN/PROG switch into the RUN position
+Select Tools->Programmer
+Select JTAG in the Mode box
#ref(Quartus_light_cdf_0.png,,50%,)
+Press Hardware Setup...
+Select USB Blaster
#ref(Quartus_Hardware_Setup.png,,50%,)
+Click Close
#ref(Quartus_light_cdf_1.png,,50%,)
+Press Start

**7.Example [#u10586aa]
***7-1.light design -complete design [#a53c1f58]
#ref(introtutorial.zip,,light)
***7-2.Full adder design - complete design [#kea162b8]
#ref(Sample.zip,,Full Adder)

//**How to make a design with a Quartus II [#kcaff22a]
//-Default window
//#ref(Quartus_main.JPG,,50%,Title);
//***Step 1 New project[#dc09ec09]
//+Click File->New Project Wizard 
//#ref(Quartus_New_Project_Wizard.png,,50%,Title)
//+If a New Project Wizard appears, click Next
//#ref(New_Project_Wizard_Intro.png,,100%,Title)
//+Type working directory, project name and top level design entity
//#ref(New_Project_Wizard_Dir.png,,100%,Title)
//+If you have source files, add them.
//#ref(New_Project_Wizard_Add.png,,100%,Title)
//+Select a target device
//#ref(New_Project_Wizard_Fam.png,,100%,Title)
//+If you want to use third party EDA tool, select it.
//-In this case, I used Model-Sim Altera
//#ref(New_Project_Wizard_EDA.png,,100%,Title)
//+If Summary appears, click finish  
//#ref(New_Project_Wizard_Sum.png,,100%,Title)

//***Step 2 Design a system [#ja466945]
//+If you want to make new design, click a &color(red,){New}; and make design 
//#ref(Quartus_test_Verilog_HDL2.png,,50%,Title)

//***Step 3 Testbench File [#i6648eee]
//+Click new
//+After New window appears, check a Verification/Debugging Files -> Vector Waveform File and click OK
//#ref(New_vwf.png,,50%,New Vector Waveform File)
//+After .vwf file appears, left click and click Insert->Insert Node or bus
//#ref(Waveform_vwf.png,,50%,)
//+After Insert Node or Bus window appears, click Node Finder
//#ref(Insert_Node_or_Bus.png,,50%,)
//+After Node Finder window appears, click List
//#ref(Node_Finder_Before.png,,50%,)
//+After interface name on the Node Finder's left, select necessary intarface and click >.
//#ref(Node_Finder.png,,50%,)
//+Click OK on Node Finder window and Insert Node or Bus window
//+After .vmf file appears, edit input data
//#ref(Waveform_vwf_middle.png,,50%,)
//#ref(Waveform_vwf_after.png,,50%,)
//+Save vmf file and File->Export vmf file to vt file
//#ref(Export.png,,50%,)
//+You can get benchmark file(vt)

//***Pin Assign [#u4f40c0d]
//+Click Assignments->Pin Planner
//+After Pin Planner window appears, select location by each interface.
//#ref(Pin_Planner.png,,50%,)

//***Step 4 Simulation [#d65bf2ee]
//+Click Assignments->EDA Tool Setting
//+After settings window appears, click EDA tool Settings
//#ref(Settings.png,,50%,Settings)
//+check Compile test bench and click Test Benches in NativeLink settings
//+After Test Benches window appears, click New
//#ref(Test_Benches_After.png,,50%,Test Benches)
//+After Test Benches window appears, click New
//#ref(New_Test_Bench_Settings.png,,50%,New Test Bench Settings)
//-Test bench name => any name
//-Top level module in test bench => you can find it in vt file using text editor. 
//-Design instance name in test bench => you can find it in vt file using text editor.
//-File name => benchmark you made

//***Step 5 Compiler a system [#j7b06a8a]
//+After you finish Step 4, click &color(red,){start compilation icon};
//+After compilation, summary will appear 
//#ref(Quartus_test_Flow_Summary2.png,,50%,)

//***Step 6 Waveform [#n7937883]
//+Click Tools -> Run EDA Simulation Tool -> EDA Gate Level Simulation
//+After ModelSim window appears, you can check a design.
//#ref(ModelSim_main.png,,50%,)

//***Other [#uf162050]
//-You can check a floor design by clicking Technology Map Viewer
//#ref(Quartus_Tech_Map_Viewer.png,,50%,Title)

//**Download a design you made to DE2 board [#z499085b]
//***Step 1 Hardware Side [#m9c068bc]
//***Step 2 Software Side [#t0a5961f]
//+Double Click Program Device
//#ref(Quartus_Program_Device.png,,50%,Title)
//+After Program Device window appears, you select hardware and mode and click Start
//-&color(red,){Driver is needed};
//#ref(Quartus_Download.png,,50%,Title)

**SOPC builder [#hf6fbb89]
-Configuration of the DE2 board with Nios2
#ref(SOPC_Config_DE2_with_Nios_2.png,,50%,)
-In this page, I make below configuration
#ref(SOPC_DE2_config_example.png,,50%,)

**1 Designing the hardware depicted above figure [#g77ab99d]
+Activation of Quartus 2
#ref(SOPC_initial_Quartus.png,,50%,)
+Select File->New Project Wizard
+New Project Wizard window appears
#ref(SOPC_New_Project_Wiz_Intro.png,,50%,)
+Click Next
+Select sopc_builder_tutorial as a working directory
+Type lights as a project name
+Automatily "lights" appears as a top-level design entity
#ref(SOPC_New_Project_Wiz_Dir.png,,50%,)
+Click Next
#ref(SOPC_New_Project_Wiz_Add.png,,50%,)
+Click Next
+Select Cyclone 2 as a Family in Device family area
+Select EP2C35F672C6 as a target device name in Available devices area
#ref(SOPC_New_Project_Wiz_Fam.png,,50%,)
+Click Next
#ref(SOPC_New_Project_Wiz_EDA.png,,50%,)
+Click Next
#ref(SOPC_New_Project_Wiz_Sum.png,,50%,)
+Click Finish
#ref(SOPC_Quartus_lights_1.png,,50%,)
+Select Tools->SOPC Builder
+Enter nios_system as the system name
+Choose Verilog as the target HDL
#ref(SOPC_SOPC_Cre_New_Name.png,,50%,)
+Click OK
#ref(SOPC_initial_SOPC.png,,50%,)
+Select Nios 2 Processor and click Add
+Choose Nios 2/e
#ref(SOPC_SOPC_Nios.png,,50%,)
+Click Finish
#ref(SOPC_SOPC_2.png,,50%,)
+Select Memory and Memory Controllers->On-Chip->On-Chip Memory(RAM or ROM) and click Add
+Set the memory width to 32 bits and total memory size to 4Kbytes
#ref(SOPC_SOPC_On_Chip_Mem.png,,50%,)
+Click Finish
#ref(SOPC_SOPC_3.png,,50%,)
+Select Peripherals->Microcontroller Peripherals->PIO(Parallel I/O) and click Add
+Specify the width of the port to be 8bits
+Choose the direction of the port to be Input
#ref(SOPC_SOPC_PIO_input.png,,50%,)
+Click Finish
#ref(SOPC_SOPC_4.png,,50%,)
+Select Peripherals->Microcontroller Peripherals->PIO(Parallel I/O) and click Add
+Specify the width of the port to be 8bits
+Choose the direction of the port to be Output
#ref(SOPC_SOPC_PIO_output.png,,50%,)
+Click Finish
#ref(SOPC_SOPC_5.png,,50%,)
+Select Interface Protocols->Serial->JTAG UART and click Add
#ref(SOPC_SOPC_JTAG_UART.png,,50%,)
+Click Finish
#ref(SOPC_SOPC_6.png,,50%,)
+Right-click on the pio_0 name and then select Rename
+Change the name to Swithches
+Right-click on the pi0_1 name and then select Rename
+Change the name to LEDs
#ref(SOPC_SOPC_7.png,,50%,)
+Select System->Auto-Assign Base Addresses
#ref(SOPC_SOPC_8.png,,50%,)
+Right-click on the cpu and then select Edit
+Select onchip_memory2_0 to be the memory device for both reset vector and exception vector
#ref(SOPC_SOPC_Nios_2.png,,50%,)
+Click Finish
#ref(SOPC_SOPC_9.png,,50%,)
+Select the System Generation tab
+Turn off Simulation. Create project simulator files
#ref(SOPC_SOPC_10.png,,50%,)
+Click Generate 
#ref(SOPC_SOPC_11.png,,50%,)
+After "SUCCESS: SYSTEM GENERATION COMPLETED" appear, click Exit
#ref(SOPC_Quartus_lights_2.png,,50%,)

**2 Integration of the Nios 2 System into a Quartus 2 Project [#k3c32d9e]
***To do list [#m632477f]
-Instantiate the module generated by the SOPC Builder into the Quartus 2 progect
-Assign the FPGA pins
-Compile the designed circuit
-Program and configure the Cyclone 2 device on the DE2 board
***2-1. Instantiation of the Module Generated by the SOPC Builder [#n0cb090c]
+Select File->New
#ref(SOPC_Quartus_New.png,,50%,)
+Select Design Files->Verilog HDL File and click OK
#ref(SOPC_Quartus_lights_3.png,,50%,)
+Copy below program and save the file called lights.v
 //Implements a simple Nios 2 system for the DE2 board
 //Inputs:  SW7-0 are parallel port inputs to the Nios 2 system
 //         CLOCK_50 are parallel port inputs to the Nios 2 system
 //         KEY0 is the active-low system reset
 //Outputs: LEDG7-0 are parallel port outputs from the Nios 2 system
 module lights(SW,KEY,CLOCK_50,LEDG);
    input [7:0] SW;
    input [0:0] KEY;
    input CLOCK_50;
    output [7:0] LEDG;
    
 //Instantiate the Nios 2 system module generated by the SOPC Builder
 //nios_system(clk, reset_n, out_port_fromm_the_LEDs, in_port_to_the_Switches)
    nios_system Nios2 (CLOCK_50, KEY[0], LEDG, SW);
 
 endmodule
#ref(SOPC_Quartus_lights_4.png,,50%,)
+Select Project->Add/Remove File in Project
+Add all *.v files produced by the SOPC Builder except for nios_system_inst.v
#ref(SOPC_Setting_Files_lights.png,,50%,)
+Click OK
#ref(SOPC_Quartus_lights_5.png,,50%,)
+Select Asignments->Import Assignment
+Select &ref(lights.csv,,lights); as File name
#ref(SOPC_Import_Assignments.png,,50%,)
+Click OK
#ref(SOPC_Quartus_lights_6.png,,50%,)
+Select Processing->Start Compilation
#ref(SOPC_Quartus_lights_7.png,,50%,)

***2-2. Programming and Configuration [#ec13e080]
+Connect the DE2 board to the host computer by means of a USB cable plugged into the USB-Blaster port.
+Turn on the power to the DE2 board.
+Ensure that the RUN/PROG switch is in the RUN position
+Select Tools->Programmer
+Select JTAG in the Mode box
+Press the Hardware Setup... 
+Select the USB-Blaster
#ref(SOPC_Programmer.png,,50%,)
+Press Start

**Nios 2 IDE 9.1 [#ua5177cb]
-Running the Application Program Using a Nios 2 Assembly Language Program 
-After you setup a hardware connection using DE2 board and host computer, you can run the assembly program.
 
***1.Starting a new project [#cd8127db]
+Activation of Nios 2 IDE
#ref(IDE_IDE_labwork_0.png,,50%,)
+Select File->New->Nios 2 C/C++ Application
#ref(IDE_New_Project_1.png,,50%,)
+Select Blank Project in Select Project Template
+Type "labwork" as a project name in Name field
+Check Specify Location
+Select a location as a working directory
+Select a &ref(labwork.ptf,,test); as a SOPC Builder System PTF File in a Select Target Hardware field.
+Automatically "cpu" appears as a CPU in a Select Target Hardware field.
#ref(IDE_New_Project_2.png,,50%,)
+Select Next
#ref(IDE_New_Project_3.png,,50%,)
+Click Finish

***2. Making an assembly file [#maab4075]
#ref(IDE_IDE_labwork_1.png,,50%,)
+After right click on the labwork project, Select New->New Source File
#ref(IDE_New_Source_File_0.png,,50%,)
+Type "labwork2.s" as a Source File (.s means assembly file) 
#ref(IDE_New_Source_File_1.png,,50%,)
+Click Finish
+Copy below a assembly program to labwork2.s
  	# Lab program for Nios-II IDE tutorial
         
         .text                   # 
 
         .global main            # makes label "main" globally known
 
 main:   movi    r10,0x41        # Load the hexadecimal value 41
                                 # to register r10
 
 loop:   mov     r4,r10          # Copy to r4  from r10
 
         nop                     # (later changed to call hexasc)
         nop                     # (later changed to mov r4, r2)
 
         movia   r15,putchar     # copy subroutine address to register
         callr   r15             # call subroutine via register
 
         addi    r10, r10,1      # Add 1 to register r10
         andi    r10, r10, 0x7f  # mask with 7 bits
         ori     r10, r10, 0x20  # set a bit to avoid control chars
 
         br      loop            # 
 
         .end                    # The assembler will stop here
         foo bar bletch          # comes after .end - ignored

***3. Compiling the assembly program [#k0ad7735]
+Focusing on a labworks2.s, Select File->Save
#ref(IDE_IDE_labwork_2.png,,50%,)
+After right click on "labwork" project, select Run As->Nios 2 Instruction Set Simulator

+After some delay, you will see the ASC2 alphabet in the Console window of the Nios 2 IDE.
#ref(IDE_IDE_labwork_3.png,,50%,)
-This is the output from your assembler program
+If a configuration and an assembler program are correct, DE2 board will display the desired work

**More information [#a000e27f]
-[[Nios II Hardware Development Tutorial>http://www.altera.com/literature/tt/tt_nios2_hardware_tutorial.pdf]]
-[[Quartus II Handbook Version 9.1 Volume 4: SOPC Builder>http://www.altera.com/literature/hb/qts/qts_qii5v4.pdf]]
-[[Quartus II Introduction Using Verilog Design>http://www.eece.maine.edu/~zhu/ece473/project/project-1/tut_intro_verilog.pdf]]
-[[Timing Considerations with Verilog-Based Designs>ftp://ftp.altera.com/up/pub/Tutorials/DE2/Digital_Logic/tut_timing_verilog.pdf]]
-[[AN 320: OpenCore Plus Evaluation of Megafunctions>http://www.altera.com/literature/an/an320.pdf]]
-[[Introduction to the Altera Nios II Soft Processor>ftp://ftp.altera.com/up/pub/Tutorials/DE2/Computer_Organization/tut_nios2_introduction.pdf]]
-[[Altera Debug Client>ftp://ftp.altera.com/up/pub/debug_client_monitor_program/tut_Altera_Debug_Client_Monitor_Program.pdf]]

SOCP_Name_Target_HDL.png SOCP_main.png Quartus_Open.png

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