3D-ONoC-Verilog の編集

[[Members-Internal]]

CENTER:SIZE(50){COLOR(green){OASIS 3D-Router Verliog HDL Source Code}}

* Source Code files Hierarchy [#c4639d5d]

CENTER:&ref(hierarchy.png,,50%);
CENTER:SIZE(20){COLOR(blue){OASIS 3D-Router files Hierarchy}}

COLOR(red){2x2x2 3D-OASIS-NoC full project} &ref(3D-OASIS-NoC.zip,,zip);

&ref(TOP_test.v,,TOP_test.v); COLOR(green){Random Number Generator Test bench}

&ref(defines.v,,defines.v); COLOR(green){define file for parameters initialization}

&ref(network.v,,network.v); COLOR(green){''Top-module: 2x2x2 mesh topology''}

- &ref(router.v,,router.v); COLOR(green){Router module}

-- &ref(input_port.v,,input_port.v); COLOR(green){Input port module}

---&ref(fifo.v,,fifo.v); COLOR(green){FIFO input buffer module}

---&ref(route.v,,route.v); COLOR(green){LA-XYZ routing module}

-- &ref(sw_alloc.v,,sw_alloc.v); COLOR(green){''Switch allocator module}
---&ref(stop_go.v,,stop_go.v); COLOR(green){Stop-Go flow control module}
---&ref(matrix_arb_formultistage.v,,matrix_arb_formultistage.v); COLOR(green){Matrix arbiter module}

-- &ref(crossbar.v,,crossbar.v); COLOR(green){Crossbar module}
---&ref(mux_out.v,,mux_out.v); COLOR(green){Crossbar module}

*OASIS 3D Code Technical Reports [#qc43ce7f]

-[[OASIS 2D Technical Report>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Mori-MS-11/m5141120_2011_MS_tr.pdf]]

-[[OASIS 3D Technical Report>http://webfs-int.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_tr.pdf]]

*Benchmark suite [#c4629d5d]
-[[JPEG; Matrix multiplication; Transpose traffic pattern; Uniform traffic pattern>http://webfs-int.u-aizu.ac.jp/~benab/doc/oasis_benchmarks_Ver.2012.pdf]];

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