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[[Members-Internal]] CENTER:SIZE(50){COLOR(green){Architecture and Design of a Router for OASIS 3D Network-on-Chip System}} CENTER:SIZE(50){COLOR(green){Architecture and Design of a, Efficient Router for OASIS 3D Network-on-Chip System}} //CENTER:&ref(pipeline.jpg,,13%); //CENTER:COLOR(green){Fig. 1 3D-OASIS-NoC system architecture} *Background [#nec7d6fe] During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures. One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research include a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations. Therefore, prototyping is an essential design phase for evaluating the performance of NoC architecture under real applications. Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [[[1>http://aslweb.u-aizu.ac.jp/aslwiki/index.php?Hiroki%20Tanaka#c4629d5d]]]. However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate. *Research goal[#mec7d6fe] The main goals of this research are: -1. Study OASIS 3D Router Architecture -2. Design the Physical router using Design Compiler (for Synthesis) and SoC Enounter (for Place and route) -3. Verify the correctness at each step using ModelSim -4. Evaluate the performance of the final 3D Router (Area, Power, and Speed) -5. Write a thesis *3D-OASIS-NoC Router Design & Simulation Workflow [#e7dd9de5] CENTER:&ref(OASIS-Router-Design-Steps.jpg,,100%); CENTER:COLOR(green){Fig. 2 3D-OASIS-NoC Router Design & Simulation Workflow} *References[#jec7d6fe] **Verilog Code [#g8eed850] -[[3D OASIS NoC Verilog HDL Code>http://aslweb.u-aizu.ac.jp/aslint/index.php?3D-ONoC-Verilog]] **Papers, Theses [#ka39bd91] -1. K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ''[[Advanced Design Issues for OASIS Network-on-Chip Architecture>http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5633769&tag=1]]'', '''IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.''' -2. [[OASIS 3D-Router Physical Design: I of III>http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_TR_June2014.pdf]], Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, June 5, 2014. -3. [[3D-OASIS-Router Physical Design:Design and Simulation>http://webfs-int.u-aizu.ac.jp/~benab/publications/treport/3D-OASIS-NoC-WOKFLOW-June2014.pdf]], Technical Report, April 1st, 2014. - 4. Kenichi Mori, [[OASIS Network-on-Chip Prototyping on FPGA>http://aslweb.u-aizu.ac.jp/aslint/index.php?Theses#n228e7d6]], '''Master's Thesis, Graduate School of Computer Science and Engineering,The University of Aizu, Feb. 2012. -5. [[K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, ''Advanced Design Issues for OASIS Network-on-Chip Architecture'',IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.>http://web-ext.u-aizu.ac.jp/~benab/publications/conferences/BWCCA10/BWCCA10-Mori.pdf]] -6. A. Ben Ahmed, On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu. [[Thesis>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11/m5141153_2011_MS_thesis.pdf]], [[slides>http://www.u-aizu.ac.jp/~benab/publications/theses/Akram-MS-11//m51411532011_MS_thesis_slides.pdf]] -7. [[About TSV: Physical design of a 3D router: reducing the number of vertical connections and enabling asynchronous Operation>https://drive.google.com/file/d/0B2HMlO4p7SuwaFV4cHp4VVdCTVE/view?usp=sharing]] **Schedule [#ucb54374] - 1. Run OASIS Tutorial: http://web-ext.u-aizu.ac.jp/~benab/publications/treport/OASIS_Router_PhysicalDesign_technical_report_2014.pdf COLOR(red){Due Date: August 23, 2014} -(2) Implementation of TVS with NanaGate Lib. [[Read This>https://drive.google.com/file/d/0B2HMlO4p7SuwaFV4cHp4VVdCTVE/view?usp=sharing]] COLOR(red){Due Date: ~ November 1st} -(3) Evaluation of OASIS 3D-Router + TSV and compare with OASIS Router (without TSV) COLOR(red){Due Date: November 2st, December 18} -(4) Thesis Writing ---- Updates: -July 18, 2014 - Ben - Added tasks
