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#author("2018-06-22T19:44:56+09:00","default:asl_member","asl_member") #author("2019-01-19T12:18:26+09:00","default:asl_member","asl_member") [[Vu Huy The]] **Step 1 COLOR(red){Due date: %%Nov.%% %%11%% %%18%%, %%30%% Dec %%5%% 8, 2016} [#fafa7c9f] -'' Step 1.1 OASIS NoC Survey'' COLOR(blue){Due date: Nov. 18 2016} [#e1465f0b] --&ref(onoc-survey-vht2016-v1.pdf,,onoc-survey-vht2016-v1.pdf); COLOR(blue){(11/11/2016, Time:12:40 PM)} --&ref(Onoc-Survey-Vht2016-V2.pdf,,Onoc-Survey-Vht2016-V2.pdf); COLOR(blue){(11/15/2016, Time:13:40 PM)} --&ref(onoc-survey-vht2016-v3.pdf,,onoc-survey-vht2016-v3.pdf); COLOR(blue){(11/18/2016, Time:16:31 PM)} --&ref(onoc-survey-vht2016-v4.pdf,,onoc-survey-vht2016-v4.pdf); COLOR(blue){(11/29/2016, Time:15:55 PM)} (&ref(oasis-noc-survey_latex.zip,,latex);) -'' Step 1.2 Compare OASIS-NoC with Conventional NoC (supporting VCs and WH)'' COLOR(blue){Due date: %%Nov. 30%%, Dec %%5%%, 8, 2016} --The following is a Verilog source code of a (conventional) router %%and a 3x3 NoC%% which implements VCs and WH. (A) &ref(https://drive.google.com/file/d/0B2HMlO4p7SuwMFlFMklwVW1lc0E/view?usp=sharing,,Verilog HDL source code of VC-WH Router/NoC); (B) [Read this RELATED reference &ref(https://drive.google.com/file/d/0B2HMlO4p7SuwTWl6VjdNOG5hXzQ/view?usp=sharing,,(Efficient_Microarchitecture_for_Netwok-on-Chip.pdf (Ph.D. Thesis, 2012.))); for details about the conventional NoC architecture.] ---1. Synthesize a conventional 3x3 NoC system (VCs and WH) with QII and extract the complexity, speed, and power. ---2. Use some benchmarks (test-benches) and evaluate the conventional 3x3 NoC system performance - bandwidth and ETE latency. ---3 %%(Option). Use a [[DE2 FPGA board>http://adaptive.u-aizu.ac.jp/?page_id=680]] and test/simulate a conventional 3x3 NoC system.%% --&ref(onoc-cnoc-study-vht2016-v1.pdf,,onoc-cnoc-study-vht2016-v1.pdf); COLOR(blue){(12/5/2016, Time:14:20 PM)} --&ref(onoc-cnoc-study-vht2016-v2.pdf,,onoc-cnoc-study-vht2016-v2.pdf); COLOR(blue){(12/8/2016, Time:14:08 PM )} (&ref(comparison-oasis-noc_latex.zip,,latex);) **Step 2 COLOR(red){Due date: Dec. %%20%% %%26%% 31, 2016} [#yc2c96e0] -''Step 2.1'' Study of Neural Network kown topology/network --Reference: ---[[''Neural Networks Fundamental''>http://www.asimovinstitute.org/neural-network-zoo/]] ---[[NN Basics>http://cs231n.github.io/neural-networks-1/]] --&ref(NeuroArch-survey-vht2016-v1.pdf,,NeuroArch-survey-vht2016-v1.pdf); COLOR(blue){(12/31/2016, Time:17:10 PM)} -''Step 2.2 Study of Neuro-inspired Computing Systems'' (survey ASIC Analog SNN/ANN; ASIC Digital SNN/ANN; FPGA SNN/ANN; DSP SNN/ANN) --References: ---[[''Artificial neural networks in hardware: A survey of two decades of progress''>https://drive.google.com/file/d/0B2HMlO4p7SuwRXduX1pkNEpLc1k/view?usp=sharing]], 2010. ---[[''Exploring the potential of brain-inspired computing''>https://drive.google.com/file/d/0B2HMlO4p7SuwQ3hkbkU2c1RMRTg/view?usp=sharing]], Ph.D. Thesis, 2015. --&ref(neuro-survey-vht2016-v1.pdf,,neuro-survey-vht2016-v1.pdf); COLOR(blue){(12/24/2016, Time:17:05 PM)} --&ref(neuro-survey-vht2016-v2.pdf,,neuro-survey-vht2016-v2.pdf); COLOR(blue){(12/31/2016, Time:17:05 PM)} -&ref(neurosystem-survey-vht2016.pdf,,neurosystem-survey-vht2016.pdf); COLOR(blue){(01/16/2017, Time:12:25 PM)} **Step 3 COLOR(red){Due date: January %%18%% 10, 2017} [#mb1d0b6c] - ''Step 3.1 Study and design in Verilog HDL only ONE Neuron Circuit''. --Use Quartus II for the synthesis of a single neuron. --The resource needed for a single neuron are: (1) A multiplication block, (2) An accumulation block, and (3) an active function block (use [[sigmoid>https://en.wikipedia.org/wiki/Sigmoid_function]] as the active function). -''Step 3.2 [[Implementation of a Simple Neural Network on DE2 FPGA board (Refer to this open source simple NN Project in VHDL)>https://github.com/ziyan/altera-de2-ann]]'' --''Note'': ''This task is also needed for your next [[COSCO>http://adaptive.u-aizu.ac.jp/?page_id=15]] Demo on Jan 18, 2017''. -&ref(ann-imp-study-vht2017-v1.pdf,,ann-imp-study-vht2017-v1.pdf); COLOR(blue){(01/10/2017, Time:18:05 PM)} **Step 4 COLOR(red){Due date: Jan. 31, 2017} [#o626d9a3] -''Step 4.1 Detailed Survey of On-chip Learning/Training Algorithms and Architectures''. COLOR(red){Focus should be on embedded vision (video) applications; precisely on object detection/classification)} ---Survey well-known algorithms and hardware for on-chip learning. ---Survey/explore the potential of on-chip learning to reveal algorithm and design needs. ---Survey fundamental learning theories, discuss numerical algorithms and their complexity in implementation. References: --[[Neuromorphic Learning VLSI Systems: A Survey>http://isn.ucsd.edu/pubs/learning_survey.pdf]] --[[''Spike Timing Dependent Plasticity (STDP'')>https://drive.google.com/file/d/0B2HMlO4p7SuwMF9WZ3pRZGs0b3c/view?usp=sharing]] --[[''Back-propagation''>https://drive.google.com/file/d/0B2HMlO4p7SuwR3p2NnhkaXd6UVE/view?usp=sharing]], --Optional: [[Hopfield>https://page.mi.fu-berlin.de/rojas/neural/chapter/K13.pdf]]; [[Boltzmann>http://deeplearning.cs.cmu.edu/notes/BM_siyuano.pdf]]; [[Probabilistic NN>http://www.uni-konstanz.de/bioml/bioml2/publications/Papers1998/BeDi98_dda_neurocomp.pdf]]; [[K-nearest neighbor (KNN)>http://www.csee.umbc.edu/~tinoosh/cmpe650/slides/K_Nearest_Neighbor_Algorithm.pdf]]; [[restricted coulomb energy (RCE)>http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.56.6648&rep=rep1&type=pdf]]; [[Region-of-Influence (ROI)>http://citeseerx.ist.psu.edu/viewdoc/download?doi=10.1.1.47.7128&rep=rep1&type=pdf]], [[Gradient-Descent (DL)>http://sebastianruder.com/optimizing-gradient-descent/]] Please upload the [[survey.pdf]] here. **COLOR(red){Jan 23 to Feb. 8, 2017 --> Return to Home Country (Holidays)} [#gbe0c4c2] **Step 5: COLOR(red){Due date: Feb. %%10%% 15, 2017} [#u339e45a] -''Complete Doctoral Research Proposal and Plan'' --Refer to [[these slides (from slide 33)>http://web-ext.u-aizu.ac.jp/~benab/publications/keynotes/BenAbdallah_PlenaryTalk_STA2016.pdf]] -&ref(DocReProPlan-vht2017-v1.pdf,,Doctoral-Research-Proposal-and-Plan-v1.pdf); COLOR(blue){(02/17/2017, Time:13:00 PM)} COLOR(red){Note: No need for a report this time. We only need slides.} %%***Step 5 COLOR(red){Due date: March %%10%% 13, 2017. (Please prepare .ppt slides and make a presentation)} [#hcfb473c]%% -''Step 5.1'' --''Describe the overall system organization'' and %%''Propose a light-weight learning algorithm for NASH System''. (NASH stands for 'Neuro-inspired ArchitectureS in Hardware' Project in ASL)%% --References: ---0. [[Spiking Deep Convolutional Neural Networks for Energy-Efficient Object Recognition>https://drive.google.com/file/d/0B2HMlO4p7SuwQXlJVkY2VjBtaUk/view?usp=sharing]], Nov. 2014. ---1. [[A Low-voltage, Low power STDP Synapse implementation using Domain-WallMagnets for Spiking Neural Networks>http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7527390]] ---2. [[FPGA-based Architecture for Real-time Synaptic Plasticity computation>https://www.researchgate.net/publication/235621751_An_FPGA_Implementation_of_a_Polychronous_Spiking_Neural_Network_with_Delay_Adaptation]] ---3. [[PhD Thesis -Theory of non-linear spike-time-dependent plasticity>https://infoscience.epfl.ch/record/85805/files/EPFL_TH3577.pdf]] ---4. [[Demonstration of STDP based Neural Networks on an FPGA>http://www-personal.umich.edu/~kulsingh/docs/stdp_on_fpga.ppt]] ---5. [[Neuron Models on FPGA, Verilog HDL>https://people.ece.cornell.edu/land/courses/ece5760/DDA/NeuronIndex.htm]] ---6.[[Design of silicon brains in the nano-CMOS era: Spiking neurons,learning synapses and neural architecture optimization>http://www.andreouandreas.com/Varia/Cassidy_Neural_Networks_2013.pdf]], A.S. Cassidy et al. / Neural Networks 45 (2013) 4–26 ---7. [[ConvNet Hardware>https://drive.google.com/file/d/0B2HMlO4p7SuwSjVCM3BCMTNYWU0/view?usp=sharing]] -''Step 5.2'' COLOR(red){Due date: April 30, 2017. Please prepare 8 to 10 pages draft and make a presentation without slides ---> Extended to May 8, 2017}. --Draft a conference paper about ''Acceleration (using FPGA) of Image Recognition with Deep Convolution Neural Network based on FT Packet Switched Network''. ---Paper of NASH-CNN COLOR(blue){(5/22/2017, Time:7:25 PM)} (&ref(20170522-NASH-CNN_Latex.zip,,latex);) ---Conf. %% http://www.mcsoc-forum.org/ %% http://www.aiccsa.net/AICCSA2017/ ***Step 6: LIF spiking neuron model, proposal of a light-weight spiking learning algorithm for NASH [#la3bff69] -''Step 6.1'': Study of CNN to SNN conversion -- Pre-trained SNN: training CNN, then applying learned weights into SNN. COLOR(blue){(7/3/2017, Time:2:00 PM)} (&ref(ANNtoSNN_survey.pdf,,pdf);) -- Directly training a SNN, COLOR(red){due date: July 24.} -''Step 6.2'': Propose and evaluate learning method for SNN in hardware, COLOR(red){due date: Aug. 28.} ***Step 7: A Scalable %%Fault-tolerant%% Multicast Routing Algorithm and Architectyure for for NASH Sytem [#c83cea93] -''Step 7.1'': Study related works, (COLOR(red){due date: Sept. 30}) -''Step 7.2'': Propose a router architecture (COLOR(red){due date: Oct. %%10%% 6}) -''Step 7.3'': Implement a whole network architecture (COLOR(red){due date: Oct. 31}) -''Step 7.4'': Evaluate the routing algorithm and write a draft conf. paper (COLOR(red){due date: Nov. %%30%% 24}) ***Step 8: An Enfficient Lighweight Fault-tolerant Multicast (3D)-Router for NASH Sytem [#p69287aa] -''Step 8.1'': Survey and report,(COLOR(red){due date: Dec. 8, 2017.}) --[[Scalable Hierarchical Network-on-Chip Architecture for Spiking Neural Network Hardware Implementations>http://ieeexplore.ieee.org/document/6322959/]], 2013 --[[Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers>http://booksc.org/dl/13555486/e871fe]], 2012 --[[An Efficient, High-Throughput Adaptive NoC Router for Large Scale Spiking Neural Network Hardware Implementations>https://ai2-s2-pdfs.s3.amazonaws.com/6483/8e37ebaf4c53d35cd623fa765c449f04fd5d.pdf]] --"Adaptive Routing Strategies for Large Scale Spiking Neural Network Hardware Implementations", Proc. 21th Int'l Conf. Artificial Neural Networks, pp. 77-84, 2011, S. Carrillo, J. Harkin, L. McDaid, S. Pande, S. Cawley, F. Morgan, --[["A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks,">https://dl.acm.org/citation.cfm?id=1592866.1592868]] International Journal of Reconfigurable Computing, vol. 2009, pp. 1-13, J. Harkin, F. Morgan, L. McDaid, S. Hall, B. McGinley, and S. Cawley, COLOR(red){Pelase make a presentaiton about this survey on Dec. 8, 2017.} ***Step 9 [#f4d1c4fe] -- Multicast Routing Algorithm paper: 1st draft version COLOR(blue){(4/11/2018, Time: 12:20 PM)} (&ref(Jnl_manuscript_draft_April10.2018.zip,,latex);&ref(Manuscript_04102018.pdf,,pdf);) -- Propose the Multicast %%Fautl-tolerance%% routing Algorithm -- Add comparison between 2D vs 3D (COLOR(red){due date April 30, 2018}). -- %%iCAST conference%% (and to Journal). ***Step 10 (COLOR(red){due date 5pm July 31, 2018)} [#ab673bac] -- Survey FT SNN -- Develop multicast faul-torance (Slide of proposed FT-KMCR, COLOR(blue){(9/21/2018, Time: 16:00 PM)} (&ref(20180919_TheHV-RPS_FT-KMCR.pptx,,pptx);&ref(20180919_TheHV-RPS_FT-KMCR.pdf,,pdf);)) -- PORT all previously developed fault-tolerant hardware machanisms to the 3DNoC-SNN -- Consider submission of this result to IEEE transaction (COLOR(red){due date by Aug 31, 2018)}
