Verilog Guideline の変更点

• 追加された行はこの色です。
• 削除された行はこの色です。
• Verilog Guideline へ行く。
• Verilog Guideline の差分を削除

#author("2019-07-03T14:39:46+09:00","default:asl_member","asl_member")
#author("2019-07-03T14:42:44+09:00","default:asl_member","asl_member")
[[NASH FPGA Prototyping]]

Website to learning writing Verilog source code

- http://www.asic-world.com/

Some problems that should be carefully understand:

[[Verilog tidbits>http://www.asic-world.com/tidbits/index.html]]

- [[Reg vs Wire>http://www.asic-world.com/tidbits/wire_reg.html]]: not all reg variable of Verilog create a real register after synthesis
- [[block vs non-blocking>http://www.asic-world.com/tidbits/blocking.html]]
- [[reset issue>http://www.asic-world.com/tidbits/all_reset.html]]

[[Sunburst design>http://www.sunburst-design.com/papers/]]

- [[reset issue>http://www.sunburst-design.com/papers/CummingsSNUG2002SJ_Resets.pdf]]
- [[full and parallel case>http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase.pdf]]

Some bugs on EDAS could be found here:
- http://www.deepchip.com/esnug.html