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#author("2019-07-05T13:32:07+09:00","default:asl_member","asl_member") #author("2019-07-12T09:46:43+09:00","default:asl_member","asl_member") CENTER:SIZE(50){COLOR(gold){NASH}:COLOR(gold){N}euro-inspired COLOR(gold){A}rchitectureCOLOR(gold){S} in COLOR(gold){H}ardware} CENTER:[[==> Main page>https://adaptive.u-aizu.ac.jp/aslint/index.php?NASH]] -Group Meeting Schedule --May 27, 2019 --June 10, 2019, 4 PM --June 24, 2019, 4PM --July 11, 2019, 4PM -- August 5, 2019, 4PM *Members [#f7385e82] -Vu -Mark -Dang (Project Manager) -Ben *Tasks [#tasks] | BGCOLOR(#87CEFA): | BGCOLOR(#87CEFA): | BGCOLOR(#87CEFA): |c | Task | Assignee | Due date | Status | | Learning using STDP | Khanh | %%13%% 11 Jul | On-going | | Re-design SNPC | Mark | %%13%% 11 Jul | On-going | | Re-design SNPC | The | %%13%% 11 Jul | On-going | | Learning using STDP | Khanh | %%11 Jul%% 5 Aug | On-going | | Re-design SNPC | Mark | %%13%% 11 Jul | Partly done | | Re-design SNPC | The | %%13%% 11 Jul | Partly done | | SNPC+NoC design | The & Mark | 5 Aug | on-going | *NASH Hardware Specificaiton [#d49fd6ab] -Vu-kun, pelase add description here *NASH Hardward Design [#ma985899] Before you intent to edit Verilog source code, please carefully check this guideline: [[Verilog Guideline]] **SNPC tile architectre and design with onchip learning [#q67e31ed] ***SNPC architecture with SRAM [#se3edaf6] --[[verilog code >https://drive.google.com/file/d/1hdBMSBsklsLRBhnFwRjKxWIMEjHTfOcQ/view?usp=sharing]], [[slides+waveform >https://drive.google.com/file/d/1m7fBzFFrDuW1cu7MfO80Ay-7xoPsmjWR/view?usp=sharing]] --SNPC Hardware Design and simulation ---Leader: Mark (please upalod your design report here) ***Converting MNIST to Spike [#a6f754aa] --[[Mathab code>https://drive.google.com/file/d/1rfdcyYoxOTYHHsqwMjujsvlhvu43O7gH/view?usp=sharing]], [[slides>https://drive.google.com/file/d/1OoD0SY3Dm33Jr7nUijsjQNwmhvACUvrY/view?usp=sharing]] ***SNPC architecture with Xbar [#o27f11b8] -to be completed ***SNPC Architecture with Learning (STDP) and SRAM/Xbar [#ca6f0869] -Current state *Refrence [#x64f1a51] ***Encoding Analog Input Data into Spike Trains [#hd682b83] Using either a rate based method, some form of temporal coding, or population coding [[reference>https://arxiv.org/pdf/1804.08150.pdf]] -[[Python code>https://github.com/Shikhargupta/Spiking-Neural-Network/tree/master/encoding]] -Verilog code *OASIS Reference [#h1e9ea10] -OASIS 2D Router (&ref(OASIS-2D.zip,,sourcecode);) -OASIS 3D Router (&ref(OASIS-3D.zip,,sourcecode);) -NI -MC Router (&ref(MCN.zip,,sourcecode);) -LIF Core (&ref(B4.Kanta Suzuki.2017.LIF Core Verilog.zip,,sourcecode);) -[[OASIS Routers Hardware Design Tutorials>http://adaptive.u-aizu.ac.jp/?page_id=592]]
