High-performance, Scalable Photonics On-chip Network for Many-core Systems-on-Chip

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Research Motivation and Goal

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Electronic packet-switched on chip interconnects alleviate the problems of poor scalability, limited bandwidth, and high power consumption in traditional designs.

However, as feature sizes continue to shrink and as we are heading towards complex and large system design consisting of hundreds of PEs, traditional design approaches may not be enough for providing significant large bandwidth with low-power consumption.

Optical Network-on-Chip (ONoC) promises significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency.

My research goal is about the development of novel routing algorithms and architecture for high-throughput Si-Photonics NoC systems.

Detailed Research Schedule

Topic TitleOverviewDue dateMaterials
Thesis submission1st draftDec.21Chapters 1-3, (PDF) Updated on: Dec.22, Time: 10:45
2nd draftDec.25Chapters 1-5, (PDF) Updated on: Dec.25, Time: 23:45
FinalDec.28Final Updated on: Dec.28, Time: 16:45
Thesis english checkingDec.30 ~Jan.3
Thesis submission to SADJan. 4(Thesis PDF- Thesis LATEX) , (Appendix PDF - Appendix LATEX) Updated on: Jan.25, Time: 7:35
Doctoral Dissertation Final ReviewJan.14

Doctoral Dissertation

Achievements

Journal papers Under Review

Conference papers Under Review

Published Papers

Journals:

Conferences:

Tutorials and Technical Reports

Materials

Miscellaneous

Photonic devices

Simulators

Links


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