Hiroki Tanaka の履歴(No.8)

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• Hiroki Tanaka へ行く。
  • 1 (2014-04-12 (土) 03:44:53)
  • 2 (2014-04-12 (土) 03:49:04)
  • 3 (2014-04-18 (金) 08:08:37)
  • 4 (2014-04-20 (日) 15:37:06)
  • 5 (2014-04-22 (火) 06:23:21)
  • 6 (2014-04-25 (金) 07:03:11)
  • 7 (2014-05-18 (日) 07:08:12)
  • 8 (2014-05-20 (火) 07:28:59)

[Members-Internal]]

First, My name is Yuki Tanaka. Not Hiroki.

Background†

During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.

One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research include a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations. Therefore, prototyping is an essential design phase for evaluating the performance of NoC architecture under real applications.

Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [1]. However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.

Research goal†

The main goals of this research are:

• 1. Study OASIS 3D Router Architecture

• 2. Design the Physical router using Design Compiler (for Synthesis) and SoC Enounter (for Place and route)

• 3. Verify the correctness at each step using ModelSim

• 4. Evaluate the performance of the final system (Area, power, latency, ...).

• 5. Write a thesis

Research plan†

Prerequisite†

References†

• K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, Advanced Design Issues for OASIS Network-on-Chip Architecture,IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.

• Guidance Lectures

• 3D-ONoC-Verilog

• A. Ben Ahmed, On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu. Thesis, slides

• R. Okada, A. Ben Abdallah,Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC Thesis, slides, Technical Report, Webpage

Benchmark suite†

• JPEG
• Matrix multiplication
• Transpose traffic pattern
• Uniform traffic pattern
  • PDF
  • ppt

My memo†

• PDF