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Background (Problem Definition)†
The huge computing power of many-core multi-processor systems will require very large on-chip and off-chip data transfer rates (> 100TB/s). One efficient technology for transmitting this level of information is the optical interconnects, which promise significant advantages over their electronic counterparts. In particular, optical on-chip interconnect (ONoC)) offers a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency. In addition, when combined with 3D integration technology, ONoC offers advantages over 2D NoC design, such as shorter wire length, higher packing density, and smaller footprint.
Understanding power and performance of Photonic Network-on-Chip is an important step towards the design of an efficient NoC system in hardware.
Sample Output
Research Goal†
The goal of this research is to study and compare power and performance of Electrical NoC with Photonic NoC using Software Simulation.
Research Schedule†
Step 0 (Mentor: D3 Achraf), Completion Date: 7/24†
- Lecture 1: Introduction to Network-on-Chip (OASIS)
- Date: Wednesday July 15: 4th period (~14:50)
- Slides: Guidance_L1 PPTX , PDF
- Lecture 2:Introduction to Photonic NoC (PHENIC)
- Date: Wednesday July 22: 4th period (~14:50)
- Slides: Guidance_L2 PPTX , PDF
Step 1 Completion Date: 7/20†
Step 2 Completion Date: 8/30†
- Simulator Installation and tools preparation.
- Install PhoenixSim in your machine and understand how it works.
Step 3 Completion Date: 10/30†
- Performance Study
- Simulate 16, 64, and 128 cores Photonic NoC and Electronic NoC systems with different benchmarks.
- Study and compare: Power, Throughput, etc.
Step 4†
Step 5†
References†
PHENIC NoC Systems Papers:
- Photonic Network-on-Chip based on Non-blocking Photonic Switch and Light-weight Electronic Router, to appear in the Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015.
- A Fault-tolerant Optical Router for Highly-reliable Low-power Mesh-based Optical Networks-on-Chip in Many-core Systems-on-Chip,to appear in the Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Oct. 9-12, 2015.
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