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| Topic Title | Overview | Start Date | Completion Date |
| Reading | Background and Related Works to Thermal and Thermal Variation Solutions | 1/25 | 2/14 |
| Create List | Discussison and Validation | 2/1 | 2/14 |
| Proposal | In-Depth summary of proposal | 4/15 | 4/21 |
| Simulation | Proposed Solution | 4/21 | 5/7 |
| First Draft | Writing of the First Draft | 5/7 | 5/20 |
| Editing | Get it finalized for publication | 5/20 | 6/1 |
Current NoC technology is limited by the speed of their buses. In order to boost the throughput and reduce the power cost of these systems, we intend to implement a Photonic Network on Chip based around the 3D Oasis NoC design.
Most proposed networks are implemented with a dedicated photonic layer stacked on top of conventional electronic layer(s). However, to satisfies future applications with high-bandwidth requirements, single-layer typologies should be modified by increasing the number of wave-guides and MRs in the photonic layer. This technique may not be suitable because of the design limitation in a single photonic router, such as number of wave-guides spacing requirement, higher wave-guides crossing loses, etc. PHENIC implements multi-layer photonic network to deal with these problems.
In addition, PNoC designs are very complex, and thus are more susceptible to physical defects and short-term malfunctions. Therefore, fault-tolerance has become a primordial requirement for these future generation high-performance systems.
Research on Reliable Photonic NoC for Many-core Systems
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