Michael Meyer の履歴(No.71)

Reliable Photonic NoC for Many-core Systems

Research Motivation†

Current NoC technology is limited by the speed of their buses. In order to boost the throughput and reduce the power cost of these systems, we intend to implement a Photonic Network on Chip based around the 3D Oasis NoC design.

Most proposed networks are implemented with a dedicated photonic layer stacked on top of conventional electronic layer(s). However, to satisfies future applications with high-bandwidth requirements, single-layer typologies should be modified by increasing the number of wave-guides and MRs in the photonic layer. This technique may not be suitable because of the design limitation in a single photonic router, such as number of wave-guides spacing requirement, higher wave-guides crossing loses, etc. PHENIC implements multi-layer photonic network to deal with these problems.

In addition, PNoC designs are very complex, and thus are more susceptible to physical defects and short-term malfunctions. Therefore, fault-tolerance has become a primordial requirement for these future generation high-performance systems.

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Research Goal†

Research on Reliable Photonic NoC for Many-core Systems

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Research Plan†

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Step 1: Completed†

Study of OASIS 3D NoC
Survey about Photonic NoC main building blocks
Survey about Photonic Switches
Survey about FT in Photonic NoC

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Step 2†

1.Development of FT switch for 3D PHENIC NoC System---Done

2.Publication of an article entitled -under submitted conference section

3.Survey about Fault Tolerant Photonic NoC. <(PDF)<(RAR).

4. TBC

5. TBC

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Step 3†

1. Run the OASIS-RV1 Tutorial

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Detailed Research Schedule†

Journal Writing

FT 2DPHENIC

8/20

9/7

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Achievement (Jnl/Conference Publications, Technical Reports, Students Guidance, Public presentations)†

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Journal papers†

None

Ongoing Jnl paper Skeleton

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papers Under Review, in preparation†

IEEE SI

<(PDF-Dec-17), <(RAR-DEC-17), Upadate: Dec. 17, 2015.

Supercomputing

<(PDF-Dec-17), <(RAR-DEC-17), Upadate: Dec. 17, 2015.

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Conference papers†

1. Michael Meyer, et al., "Microring Fault-resilient Optical Router for Reliable Network-on-Chip Systems," in Proc. of 9th IEEE International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-15), Turin, Italy, Sept. 2015, pp. 227-234.
- //MCSoC15_CRP_Final.pdf; //MCSoC2015_CRP_Final.Latex, July 6 17:00}

MCSoC15_Published.pdf; MCSoC15_Slides.pdf;

2. M. Meyer, et al., "On the Design of a Fault-tolerant Photonic Network," in the Proc. of the IEEE International Conference on Systems, Man, and Cybernetics (SMC2015), Hong Kong, Oct. 9-12, 2015, pp 821-826.

SMC2015_CRP_final.pdf; SMC2015_CRP_final.Latex, July 16 16:10}

SMC2015_Published.pdf; SMC2015_POSTER.pdf, OCT 15 15:10}

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Technical Reports†

None

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Public Presentation @ Conferences†

June 5, 2015. Research Progress Presentation

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Progress reports†

(May 22), Time: 5:17 PM.
(June 3), Time: 3 PM.

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Related References†

12. A Fault-Tolerant Routing Algorithm Design for On-Chip Optical Networks, Reliable Distributed Systems (SRDS), 2013 IEEE 32nd International Symposium on Sept. 30 2013-Oct. 3 2013.

Custom Integrated Circuits Conference (CICC), 2011 IEEE, pp. 1-8, Sept. 2011.

11. Reliability-Performance Trade-offs in Photonic NoC Architectures, MS Thesis, 2013, Rochester Institute of Technology, Rochester, NY.

Related paper: Performance evaluation of reliability aware photonic Network-on-Chip architectures, Green Computing Conference (IGCC), 2012 International.
- BER-based Power Budget Evaluation for Optical Interconnect Topologies in NoCs, Proceedings of the IEEE International Symposium on Circuits and Systems, ISCAS 2012.
- BER (bit-error-rate), BER (bit error ratio), BEP (bit error probability)

10. TSV

9 A. Biberman et. al, first experimental bit-error rate validation of 12.5-Gb/s silicon modulator enabling photonic networks-on-chip, in IEEE /OSA Opt. Fiber Conf., 2010.

8. I. Datta et al., "Design Methodology for Optical Interconnect Topologies in NoCs With BER and Transmit Power Constraints," in IEEE/OSA JLT, 2014

7. Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 10, OCTOBER 2011

6. Recommended Reading 1

5. A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip, GLSVLSI '14 Proceedings of the 24th edition of the great lakes symposium on VLSI Pages 267-272,2014

4. OASIS Network-on-Chip Prototyping on FPGA, '''Master's Thesis, Graduate School of Computer Science and Engineering,The University of Aizu, Feb. 2012.

3. Architecture and Design of 3D Network-on-Chip, '''Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012.

2. Advanced Design Issues for OASIS Network-on-Chip Architecture, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, -Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.

1. Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2012, Ref. 16RO-GT09

. E-Books

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Related Projects†

PHENIC

OASIS

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OASIS 3D-Router†

Verilog Source Code
- 3D-OASIS NoC Verilog HDL Code

Physical Design
- OASIS 3D-Router Physical Design Tutorial, July 2014.

VLSI@ASL

Updates:

B., April 3, 2015 - Publication schedule added.
B., Nov. 9, 2014 - updated research progress tasks
Ben, Oct. 20, 2014 - added Ref. # 10.
Ben, July 17, 2014 - added Ref. 8 and 9, added OASIS Tutorial
Ben,27/05/14
Ben,20/05/14
Ben,12/04/14