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The biological brain implements massively parallel computations using a complex architecture that is different from current Von Neuman machine. Our brain is a low-power, fault-tolerant and high-performance machine! It consumes only about 20W and brain circuits continue to operate as the organism needs even when the circuit (neuron, neuroglia, etc.) is perturbed or died.
Conventional neural networks encode information with static input coding, eg. encoding a pattern as 0011 (binary bits) for 4 input neurons, and another pattern 0010. While in SNN, besides the pattern code, the time-related factors, eg. spiking rate, spiking rank and spiking intervals, can be used to present the information. This greatly increases the information processing capacity of a neural network.
SNN only process information when spikes occur. As a result, SNNs consume almost no energy when no spikes occur [www]. A biological SNN (e.g. mammalian brains) uses a spike rate of only several KHz to finish a complex task (e.g. vision pattern recognition) with each spike consumes an energy of in fJ per synapse.
Spiking neural network (SNN) simulations are a flexible and powerful method for investigating the behavior of neuronal systems. However, simulation of the spiking neural networks in software is slow. An alternative approach is a hardware implementation of such system, which provides the possibility to generate independent spikes accurately and simultaneously output spikes in real time. Also, the spiking neural network can take full advantage of hardware inherent parallelism. SNN and ANN are widely used in signal processing, speech synthesis, pattern recognition, and so forth.
When the system is implemented in FPGA/hardware, there are several aspects of computer arithmetic that need to be considered; these include data representation, inner product computation, implementation of activation functions, storage and update of weights, and the nature of learning algorithms.
The design of NNs is mainly focused on the following three aspects: neuron models, the topology of NNs, and the learning algorithm.
The goal of this Doctoral thesis is to research and implement an adaptive and low-power Deep Spiking Neural Networks Processor based on the OASIS Scalable Packet-Switched Network. In particular, the research consists of:
