Vu Huy The の履歴(No.7)

NASH: Neuro-inspired ArchitectureS in Hardware Project

Doctoral Topic: Adaptive Highly Reconfigurable Deep Learning Processor for Spiking Neural Networks with Scalable Packet-Switched Network

Background †

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Research Goal†

The goal of this Doctoral thesis is to research and implement an adaptive and low-power Deep Spiking Neural Networks Processor based on the OASIS Scalable Packet-Switched Network. In particular, the research consists of:

(1) An efficient adaptive configuration method which enables reconfiguration of different SNN parameters (spike weights, routing, hidden layers, topology, etc.)

(2) A mixture of different Deep NN topologies (CNN and RNN) shall be investigated

(3) An Efficient Multicast Fault-tolerant Routing Algorithm for the neurochip

(4) Efficient on-chip learning Algorithm

(5) To demonstrate the performance of the algorithms and the system, an FPGA implementation shall be developed and interfaced to a small drone. In addition, a VLSI implementation shall be also developed.

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Research schedule†

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Oct. to Feb. 2017 †

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Step 5 Due date: March 10 13, 2017. (Please prepare .ppt slides and make a presentation)†

Step 5.1
- Describe the overall system organization and Propose a light-weight learning algorithm for NASH System. (NASH stands for 'Neuro-inspired ArchitectureS in Hardware' Project in ASL)

References:

0. Spiking Deep Convolutional Neural Networks for Energy-Efficient Object Recognition, Nov. 2014.

1. A Low-voltage, Low power STDP Synapse implementation using Domain-WallMagnets for Spiking Neural Networks

2. FPGA-based Architecture for Real-time Synaptic Plasticity computation

3. PhD Thesis -Theory of non-linear spike-time-dependent plasticity

4. Demonstration of STDP based Neural Networks on an FPGA

5. Neuron Models on FPGA, Verilog HDL

6.Design of silicon brains in the nano-CMOS era: Spiking neurons,learning synapses and neural architecture optimization, A.S. Cassidy et al. / Neural Networks 45 (2013) 4–26

7. ConvNet Hardware

Step 5.2 Due date: April 30, 2017. Please prepare 8 to 10 pages draft and make a presentation without slides.

Draft a conference paper about Acceleration (using FPGA) of Image Recognition with Deep Convolution Neural Network based on FT Packet Switched Network.
- Conf. http://www.mcsoc-forum.org/

References: