Pig Recognition on FPGA using Deep Convolution Neural Network

Leader: M1 Ryunosuke Murakami

Background and Motivation

Deep Neural Networks have been proved to be powerful tools for real world applications/tasks, such as pattern recognition, classification, regression, and prediction. However, simulating a large network in real-time requires high-performance machines or accelerators. Typical accelerators for large-scale NN accelerators use GPUs or ASIC chips. While ASICs deliver high performance, they lack the flexibility to reconfigure and hence are unable to adapt variation in the design and models employed. GPUs have better speedup over multi-core CPUs and good flexibility, but it lacks scalability to handle larger networks.

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Goal and Expected output

The goal of this research is to implement a Pig Face Recognition on FPGA using Deep Convolution Neural Network to be integrated in OASIS-FMS1 system.

References

Special seminar

RPR

RPS

Step 1 Due Date: March 27, 2017, 16:00 -


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