OASIS-8C System の履歴(No.7)

OASIS-8C: Verilog Design and FPGA Prototyping of 8-core OASIS Network-on-Chip System

Project Goal†

Real design in verilog HDL and prototyping on FPGA of a small scale 8-core OASIS Network-on-Chip System.
Detailed Design Manual.

System specifications:
- OASIS 3D Network-on-Chip [Ref.1].
- Network Interface: [Ref.2].
- Processing Elements:
  - CPU: MIPS
  - MEM: On-chip (verilog code), Off-chip (see I/O).
  - I/O: Off-chip Memory, Display (LCD, LED), Inter-connection (UART/USB/PCI).
Application specifications:
- Target CPU: MIPS.
- Target applications: TBD.
Implementation environment:
- Language: Verilog HDL.
- Simulation tool: Modelsim Altera.
- Implementation tool: Altera Quartus II.
Implementation board: Spartan DE II.
- Resource:
  - Logic:
  - Register:
  - I/O:
  - External devices:
- Note:

Step 01: Design Preparation.
- Decide the system's specification.
- Prepare the required tools, boards and source code.
Step 02: Individual Network Tile (PE-NI-R) Implementation.
- Establish an individual network tile: PE(Processing Element) - NI(Network Interface) - R(Router).
- I/O Interface connection.
- Connection synchronization.
- Demo application implementation on FPGA.
Step 03: 2D 2x2 Network Implementation.
- Establish a 2D 2x2 Network Implementation (2 CPUs, 1 Memory, 1 I/O).
- Demo application implementation on FPGA.
Step 04: 3D 2x2x2 Network Implementation.
- Establish the proposal architecture.
- Demo application implementation on FPGA.

Table of schedule

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