NASH FPGA Prototyping の履歴(No.7) - ASL Wiki

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NASH:Neuro-inspired ArchitectureS in Hardware

Meeting Schedule:

May 27, 2019 - SNPC and STDP
June 10, 2019, 4 PM

HARDWARE Design†

LIF†

SNPC with one Neuron†

SNPC with Xbar†

3D-NoC Interconnect†

Encoding Analog Input Data into Spike Trains†

Using either a rate based method, some form of temporal coding, or population coding reference

Python code
Verilog code

Reference†

OASIS 2D Router (sourcecode)
OASIS 3D Router (sourcecode)
NI
MC Router (sourcecode)
LIF Core (sourcecode)
OASIS Routers Hardware Design Tutorials