Real-time Spiking Neuromorphic Architecture/Chip with Efficient On-chip Learning for Deep Neural Networks
Research Background†
TBA
Research Goal†
The goal of this Doctoral thesis is to research and implement a Deep Spiking Neural Network Architecture with on-chip learning scheme and based on the previously developed schemes NASH1
The expected outputs from this research are:
- (1) An efficient adaptive configuration method which enables reconfiguration of different SNN parameters (spike weights, routing, hidden layers, topology, etc.)
- (2) An Efficient Multicast Fault-tolerant Routing Algorithm for the neurochip
- (3) Efficient on-chip learning Algorithm
- (4) To demonstrate the performance of the algorithms and the system, an FPGA implementation shall be developed and evalauted with several biological SNNs. In addition, a VLSI implementation shall be also developed.
TBA.
Research schedule†
Step 1: READING and SURVEY†
- Conclude Reading 2, SNN Learnign Algorithms and Hardware Implementation Survey
- Finalyse the Readig 2, Report about NN Learning Survey (May 29, 2019, 11:00 AM)
- Run the following SNN Simulator and investigate its performance and the STDP leanring mechanism
Achievement†
On-going Conference and Jnl papers†
Conferences†
Journals†
Survey reports†
Doctoral Dissertation†
Update History†
- May 6, 2019: Schedule updtaed, by B.
- April 17, 2019: Page created, by B.
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