Available Research Topics の履歴(No.7) - ASL Wiki

[ トップ ] [ 新規 | 一覧 | 検索 | 最終更新 | ヘルプ ]

- References:
  - Phython http://pythonvision.org/basic-tutorial/
  - Modelsim/MATLAB Co-simulation of a QoS Multi-Core Image Processing System using on-Chip Interconnect.

- Ref.:

- References:

References:

PHENIC:Si-Photonics NoC †

References:
- A.Ben Ahmed, M.Meyer, Y.Okuyama, A.Ben Abdallah, "Efficient Router Architecture, Design and Performance Exploration for Many-core Hybrid Photonic Network-on-Chip (2D-PHENIC)", submitted to the 2014 International Conference on Information Science and Control Engineering ICISCE 2015, Shanghai, China, April 24-26, 2014 (Latex) (PDF)

Achraf Ben Ahmed, A. Ben Abdallah, PHENIC: Towards Photonic 3D-Network-on-Chip Architecture for High-throughput Many-core Systems-on-Chip, IEEE Proceedings of the 14th International conference on Sciences and Techniques of Automatic control and computer engineering, Dec. 2013. DOI

References:

Achraf Ben Ahmed, Akram Ben Ahmed, A. Ben Abdallah, Novel Si-Photonics Network-on-Chip for Future Generations of Many-core Systems-on-Chip, submitted to (Journal of Parallel and Distributed Computing)(PDF),(Latex).

Achraf Ben Ahmed, Akram Ben Ahmed, Y.Okuyama, A. Ben Abdallah, Low-overhead Path-setup Algorithm for Energy-efficient Hybrid Silicon-Photonic Network-on-Chip Systems, submitted to The IEEE 7th International Conference on Awareness Science and Technology (ICAST 2015) (PDF , Latex).

GT 3. Hardware Design of High-speed Optical Router Architecture for PHENIC Many-core Systems

References:

OASIS NoC Project

Abderazek Ben Abdallah, Mitsuhiro Nakamura, Akram Ben Ahmed, Yuichi Okuyama, Fault-tolerant Router for Highly-reliable Many-core 3D-NoC Systems, The 3rd International Scientific Conference on Engineering and Applied Sciences (ISCEAS 2015), July 29-31, 2015, Okinawa, Japan.

Akram Ben Ahmed, OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, University of Aizu, July 8, 2014.

OASIS: Reliable Network-on-Chip †

5. Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, B4 Mitsunari Ishii (COMPLETED)

6. Design and Evaluation of 3D-OASIS-NoC Matrix Processor,

7. Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV),

8. Error Detection & Correction Mechanism Based on Router-to-Router Approach

Processing Cores for Adaptive computing †

Adaptive Processor
- Implementation of task assignment algorithm
- Implementation of architecture (Ishikuro)
Matrix Processor
- Layout design of Matrix-ALU
- Practical interface between host computer/routers (Nakamura)
- Embedded navigation system as a practical application (Yusuke)

Advanced Vision Processing Algorithms†

Architecture exploration of 2DCDP for 3D-chips
Video recognition with TSCDP (Hayamizu)

Real Time Signal Processing†

Extraction of training efficiency from EEG (Ito)
P300 detection from few electrodes