Members-Internal
Efficient Error Detection Mechanism for OASIS Network-on-Chip System
3D-OASIS-NoC flit format
Contents:
Background†
During the past decade, 3D-Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC systems. At the same time, concerns about their reliability have grown as well due to the different kinds of faults that these systems may encounter. Therefore, 3D-NoC must be fault-tolerant to any kind of permanent failure or run-time malfunction. To achieve this goal, a fault-detection scheme is necessary to discover the presence of fault before the propagation of the fault into the entire system and cause the its collapse.
Previously, 3D-Fault-Tolerant-OASIS (3D-FTO) has been designed. 3D-FTO is able to recover from a large number of faults that can occur at links, input-buffers, and crossbar. However in this system, a fault detection mechanism is absent and the diagnosis of faults rely on assuming the presence of faults at a certain period of time. This make the fault recovery less efficient and diminish the reliability of the system.
Problems and Motivation†
In our previous research, a Network Interface (NI) to enhance the reliability of 3D-FTO system was presented. In the
proposed NI, an End-to-End error-detection mechanism based on Cyclic Redundancy Check (CRC) was implemented. However, this mechanism suffers from several problems:
- When using End-to-End detection, the fault occurrence can be detected; however, it cannot be localized. Therefore, the fault diagnosis phase cannot be achieved.
- At the detection of fault, the transmitter NI resends the flits along the same path already detected faulty. Consequently, the resent flit follows the same faulty path; thus, creating a significant latency and power overheads. Furthermore, the flit might not reach its destination, especially when the detected fault is permanent and cannot be recovered.
- In case where a fault occurs at the first hops, it is only detected at the receiving NI. This results in an increasing end-to-end latency since the flit has to travel many hops to the destination and then resent again, even when the fault is in the first hop.
- The previously proposed scheme can detect the presence of fault; but, it cannot recover from it.
- The verification was made using test-benches with small Random-Number-Generator application without using real processors running real applications.
Research goal†
The main goal of this research is to design and implement a fault detection and correction scheme for 3D-Fault-Tolerant-OASIS (3D-FTO). The scheme is based on Error-Detection-Codes (EDC) and Error-Correction-Codes (ECC). It should detect the presence of any kind of errors or malfunction and make the necessary communications with the different modules of 3D-FTO to perform the quick recovery ensuring a graceful performance degradation as less as possible. In addition, the proposed scheme is implemented and tested on a 2x2x2 network using MIPS cores attached to 3D-FTO and running real applications.
Research plan†
- Investigate about the different approaches for fault detection in NoC systems
- Understand Mr. Ishii's work
- Understand 3D-FTO architecture.
- Modify the flit format to host the additional code portion for fault detection and correction.
- Make the necessary modification for the remaining modules of the router.
- Evaluate the performance of the scheme (Area, power, latency, ...)
To be continued
References†
- Mitsunari Ishii, Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. slides.pdf, Thesis.pdf, Technical Report.pdf,
- Run this Tutorial on your machine.
OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.
Backup†
![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
