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With the increasing demand for computing machines that more closely model the biological brain, the field of neuro-inspired computing has progressed to the exploration of Spiking Neural Networks (SNN). SNN is the third generation of the computing paradigm "Neuro-inspired computing", modeled after the neural networks of the biological brain to best the setbacks of conventional Von Neumann architecture. This computing paradigm tries to model specifications that make the biological brain achieve rapid parallel computations in real-time, fault tolerance, power efficiency, and the ability to perform tasks like image recognition and language learning, that the conventional computing machine cannot. Unlike its predecessors, the neurons in SNN mimic the information transfer in biological neurons (event triggered), and this immensely enhances its performance.
It has been understood that spiking neural networks (SNNs) and synaptic devices can achieve high energy efficiency and fault tolerance in complex tasks by emulating biological neurons and synapses. Hence, they have a big potential for the replacement of traditional von Neumann computers. [WWW.ref].
SNNs can achieve better power efficiency when more powerful encoding methods are applied, or when SNNs are optimized for short latency. Second, the inference results in SNNs can be gotten faster than ANNs, though the precision may be lower. The inference precision would then rise with more evidence accumulated over time Ref. Spiking neurons are only activated when sufficient signals are integrated from other neurons, therefore the neural activities at the network level are usually sparse, which can make executing SNNs by matrix-based operation on a traditional CPU or GPU inefficient.Ref.
Neuromorphic hardware is designed to accelerate the running of SNNs by allocating spiking neurons and synapses to neuromorphic chips and it can increase the power efficiency of SNNs by event-based computing.
The goal of this Doctoral thesis is to research and implement a Deep Spiking Neural Network Architecture with on-chip learning scheme and based on the previously developed schemes NASH1
The expected outputs from this research are:
| Date | Task |
| ☑️April 1st 2019 - August 30, 2019 | Survey, etc. |
| ☑️September 1st, 2019 - July 31,2020 | Complete SNPC on-chip learning with STDP |
| September 11, 2020 | JoS paper draft |
| August 16, 2020 to September 11, 2020 | Understand and run demo of k-means clustering based fault-tolerant multicast spike routing algorithm |
| August 16, 2020 to September 11, 2020 | Replace spike injector with SNPC and run again the demo of k-means clustering based fault-tolerant multicast spike routing algorithm |
| September 1, 2020 to December 31, 2020 | Integrate SNPC into 3D-NoC architecture |
| September 1, 2020 to December 31, 2020 | Write and submit journal paper on the 3D-NoC SNN |
| January 1, 2021 to March 31, 2021 | Explore reconfigurability of neuron model and learning algorithm on SNPC |
| February 1, 2021 to March 31, 2021 | Write and submit a confenence paper on reconfigurable 3D-NoC SNN |
| April 1, 2021 to June 30, 2021 | Explore Fault tolerance in the reconfigurable and non reconfigurable 3D-NoC SNN |
| June 1, 2021 to August 31, 2021 | Write and submit a journal paper on a faul tolerant reconfigurable 3D-NoC SNN |
| September 1, 2021 to March 31, 2022 | Explore Biological SNNs. |
