Research on Fault-tolerant Spiking Neuromorphic System based on Packet Switched On-chip Network & On-chip Learning

Research Background†

With the increasing demand for computing machines that more closely model the biological brain, the field of neuro-inspired computing has progressed to the exploration of Spiking Neural Networks (SNN). SNN is the third generation of the computing paradigm "Neuro-inspired computing", modeled after the neural networks of the biological brain to best the setbacks of conventional Von Neumann architecture. This computing paradigm tries to model specifications that make the biological brain achieve rapid parallel computations in real-time, fault tolerance, power efficiency, and the ability to perform tasks like image recognition and language learning, that the conventional computing machine cannot. Unlike its predecessors, the neurons in SNN mimic the information transfer in biological neurons (event triggered), and this immensely enhances its performance.

It has been understood that spiking neural networks (SNNs) and synaptic devices can achieve high energy efficiency and fault tolerance in complex tasks by emulating biological neurons and synapses. Hence, they have a big potential for the replacement of traditional von Neumann computers. [WWW.ref].

SNNs can achieve better power efficiency when more powerful encoding methods are applied, or when SNNs are optimized for short latency. Second, the inference results in SNNs can be gotten faster than ANNs, though the precision may be lower. The inference precision would then rise with more evidence accumulated over time Ref. Spiking neurons are only activated when sufficient signals are integrated from other neurons, therefore the neural activities at the network level are usually sparse, which can make executing SNNs by matrix-based operation on a traditional CPU or GPU inefficient.Ref.

Neuromorphic hardware is designed to accelerate the running of SNNs by allocating spiking neurons and synapses to neuromorphic chips and it can increase the power efficiency of SNNs by event-based computing.

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Research Goal†

The goal of this Doctoral thesis is to research and implement a Deep Spiking Neural Network Architecture with on-chip learning scheme and based on the previously developed schemes NASH1

The expected outputs from this research are:

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Research Schedule†

DateTask
Complete on-chip learning with STDP
write and submit conference paper
July 1, 2020 to December 31, 2021Integrate SNPC into 3D-NoC architecture
September 1, 2020 to January 20, 2021Write and submit journal paper
April 1, 2021 to September 30, 2021Explore Fault tolerance in the SNPC and in the entire 3D-NoC SNN
April 15, 2021 to August 31, 2021Write and submit a journal paper
October 1, 2021 to April 28, 2022Explore Biological SNNs.
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Research Progress - ===> previous tasks†

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Hardware Implementation of learning algorithm on SNPC†

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Research Progress Seminar†

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Achievement†

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new paper†

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Published papers†

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Design and Evaluation of SNPC for (IEEE_BigCom2020) conference. Full paper submisison due date: Sept 30, 2019†

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The ACM Chapter International Conference on Educational Technology, Language and Technical Communication (ETLTC). Full paper submisison due date: Nov. 19, 2019†

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My Shared Google Drive Folder†

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Update History†

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