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With the advance in microprocessor technology, demands for practical vision and image recognition applications have been appearing in automobile, security, surveillance, and robot applications. Processing multi-objects recognition require higher computing power, making it difficult to perform the computation on conventional shared bus general-purpose processors, despite the recent dramatic improvements in processor performance. Therefore, specialized architecture for communication and computation are needed for high-performance image recognition tasks. Three dimensional Networks-on-Chip (3D-NoC) has been proposed as a promising architecture which combines the high parallelism of Network-on-Chip (NoC) interconnect paradigm with the high-performance and lower interconnect-power of 3-dimensional integration circuits. However, as 3D-NoCs keep showing their advantages against 2D-NoC architectures, their reliability is put under question
The main goal of this project is to research about algorithms and, architecture for a Reliable Many-core 3D-NoC System Targeted for Real-Time Vision Applications (i.e., gesture/motion/object recognition/surveillance). The system is based on our earlier developed reliable Network-on-Chip (OASIS). The system will integrate several dedicated PEs for ILP/Data/Thread level parallelism, while the 3D-OASIS NoC orchestrates communications between PEs and is used for large amount of data transactions among tasks.
Update: Dec. 1, 2014 - B.
