![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
Feed Forward Neural Networks (FFNN) when designed to work with floating point (FP) precision performs a large number of elementary products and sums. For each neuron of FFNN within the hidden layers, a non-linear function computation is required to determine the activation value of the neuron. Without efficient, dedicated FP hardware, such computations can create difficulties for the whole system performance of the system, hence making the design difficult to be used in critical applications like real-time systems.
The goal of this research is to implement a Feed Forward Neural Networks (FFNN) with floating point on FPGA. A real application, such as character recognition, should be demonstrated. The FFNN should be trained in Matlab environment and the Nios II/f (co cache) should be used for Altera FPGA prototyping. The Nios II ISA should be extended to have a Floating Point ALU.
