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Efficient Error Detection and Correction Mechanism for OASIS Network-on-Chip System
3D-OASIS-NoC flit format
Contents:
Background†
During the past decade, 3D-Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-NoC systems. At the same time, concerns about their reliability have grown as well due to the different kinds of faults that these systems may encounter. Therefore, 3D-NoC must be fault-tolerant to any kind of permanent failure or run-time malfunction. To achieve this goal, a fault-detection scheme is necessary to discover the presence of fault before the propagation of the fault into the entire system and cause the its collapse.
Previously, 3D-Fault-Tolerant-OASIS (3D-FTO) has been designed. 3D-FTO is able to recover from a large number of faults that can occur at links, input-buffers, and crossbar. However in this system, a fault detection mechanism is absent and the diagnosis of faults rely on assuming the presence of faults at a certain period of time. This make the fault recovery less efficient and diminish the reliability of the system.
- Network on chip
- Network on Chip (NoC) has become an attractive option for solving the problems of bus-based systems. The basic idea of NoC is that the processor is connected to a packet-switched network which is similar to the way computers are connected to the Internet. NoC is a paradigm of great potential for solving complex processes, which is easily configured.
- Fault-tolerance
- 3D-Network-on-Chips (3D-NoCs) have been showing their advantages against 2D-
NoC systems. At the same time, concerns about their reliability have grown as well due to the different kinds of faults that these systems may encounter. Therefore,
3D-NoCs must be fault-tolerant to any kind of permanent failure or run-time malfunction. To achieve this goal, a fault - detection scheme is necessary to discover the presence of faults before its propagation into the entire system that causes its collapse.
Research goal†
The main goal of this research is to design and implement a fault detction and correction scheme for 3D-Fault-Tolerant-OASIS (3D-FTO). The scheme is based on Error-Detection-Codes (EDC) and Error-Correction-Codes (ECC). It should detect the presence of any kind of errors or malfunction and make the necessary communications with the different modules of 3D-FTO to perform the quick recovery ensuring a graceful performance degradation as less as possible.
Prev research(Mr,Ishii work)†
- What
- Implement end to end error detection mechanism(CRC) for 3D OASIS NoC
- Problems
- End to end mechanism, so it is not very effective
- Simulation network size is small
- Verification by simulation only(using test bench)
Proposal†
- Implement router to router error detection mechanism for 3D OASIS NoC
- Do simulation in a large network size
- Actually verified using a real processor
Research plan†
- Investigate about the different approaches for fault detection in NoC systems
- Understand 3D-FTO architecture.
- Modify the flit format to host the additional code portion for fault detection and correction.
- Make the necessary modification for the remaining modules of the router.
- Evaluate the performance of the scheme (Area, power, latency, ...)
References†
- Mitsunari Ishii, Design and Evaluation of Efficient Error Detection Mechanism for OASIS 3D-NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. slides.pdf, Thesis.pdf, Technical Report.pdf,
- Run this Tutorial on your machine.
OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.
Backup†
![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
