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Current NoC technology is limited by the speed of their buses. In order to boost the throughput and reduce the power cost of these systems, we intend to implement a Photonic Network on Chip based around the 3D Oasis NoC design.
Most proposed networks are implemented with a dedicated photonic layer stacked on top of conventional electronic layer(s). However, to satisfies future applications with high-bandwidth requirements, single-layer typologies should be modified by increasing the number of wave-guides and MRs in the photonic layer. This technique may not be suitable because of the design limitation in a single photonic router, such as number of wave-guides spacing requirement, higher wave-guides crossing loses, etc. PHENIC implements multi-layer photonic network to deal with these problems.
In addition, PNoC designs are very complex, and thus are more susceptible to physical defects and short-term malfunctions. Therefore, fault-tolerance has become a primordial requirement for these future generation high-performance systems.
Research on Reliable 3D Photonic NoC for Many-core Systems
| Old Phenic Simulation | PhoenixSim | 5/20 | 6/2 |
| Simulation of Fult Recovery | PhoenixSim | 6/2 | 6/10 |
| Conference paper Writing | 2DFTTDOR | 6/10 | 6/20 |
| Conference paper Editing | 2DFTTDOR | 6/20 | ** |
| Simulation In greater Detail | Add in Multiple Recovery options | 6/20 | 7/15 |
| Journal Writing | FT 2DPHENIC | 7/15 | 7/30 |
| Journal Editing | FT 2DPHENIC | 7/30 | ** |
| Fault Detection | FT 2DPHENIC | 8/1 | 8/15 |
Updates:
