Fault-tolerant Spiking Neuromorphic System based on 3D-NoC and On-chip Learning

Research Background†

With the increasing demand for computing machines that more closely model the biological brain, the field of neuro-inspired computing has progressed to the exploration of Spiking Neural Networks (SNN). SNN is the third generation of the computing paradigm "Neuro-inspired computing", modeled after the neural networks of the biological brain to best the setbacks of conventional Von Neumann architecture. This computing paradigm tries to model specifications that make the biological brain achieve rapid parallel computations in real-time, fault tolerance, power efficiency, and the ability to perform tasks like image recognition and language learning, that the conventional computing machine cannot. Unlike its predecessors, the neurons in SNN mimic the information transfer in biological neurons (event triggered), and this immensely enhances its performance.

It has been understood that spiking neural networks (SNNs) and synaptic devices can achieve high energy efficiency and fault tolerance in complex tasks by emulating biological neurons and synapses. Hence, they have a big potential for the replacement of traditional von Neumann computers. Commonly, the implementation technology for an SNN can be categorized into synaptic materials and devices, integrating memory, on-line learning elements, analog circuits, and digital computing structures. The complexity of an SNN architecture is mainly dependent on the number of electronic synapses that form active neuronal links between artificial neurons [WWW.ref].

Hardware implementations (neuromorphic chips) that do not have the architectural limitation of the Von Neumann architecture, and aim at taking advantage of the sparsity of Spikes in SNN to reduce power, are presented as an alternative.

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Research Goal†

The goal of this Doctoral thesis is to research and implement a Deep Spiking Neural Network Architecture with on-chip learning scheme and based on the previously developed schemes NASH1

The expected outputs from this research are:

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Research Schedule†

DateTask
May?? to June ??, 2020Complete on-chip learning with STDP
--write and submit conference paper
-Explore reconfigurable learning and reconfigurable Neuron on the SNPC
--Write and submit conference paper
-Integrate SNPC into 3D-NoC architecture
--Write and submit journal paper
-Explore applications and application mapping for 3D-NoC SNN
--Write ans submit journal paper
-Explore Fault tolerance in the SNPC and in the entire 3D-NoC SNN
--Write and submit a journal paper
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Research Progress - ===> previous tasks†

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Hardware Implementation of learning algorithm on SNPC†

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Achievement†

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new paper†

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Published papers†

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Design and Evaluation of SNPC for (IEEE_BigCom2020) conference. Full paper submisison due date: Sept 30, 2019†

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The ACM Chapter International Conference on Educational Technology, Language and Technical Communication (ETLTC). Full paper submisison due date: Nov. 19, 2019†

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My Google Shared Folder†

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Update History†

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