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FPGA-based Acceleration of Deep Neural Networks

CENTER:Optimization and Design of a Brain-inspired Architecture on FPGA for Traffic Light Detection

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Motivation and Background†

In recent years, the advance of software-based AI (artificial intelligence) has increased the demand for realization of power-efficient and fast AI computing hardware devices and systems overcoming the bottleneck of the conventional Von Neuman computing style. The brain-inspired cognitive computing in both learning and inference tasks. In SNN, besides the pattern code, the time-related factors,eg.spiking rate (frequency), spiking rank and spiking intervals, are generally used to present the information. The human brain is fault-tolerant and continuously adapting a changing environment. Spiking Neural network have many models such as Integrate and Fire(IF), Leaky Integrate and Fire(LIF),Hodgkin Huxly Model(HH), and so on. In some Application, it occurs some faults such as sensor data noises in Unmanned Aerial Vehicles. The features of SNN can be found in repairing such faults.

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Research Goal†

This study provides a decision of efficient fault-tolerant algorithm and experiments how SNN repair itself from faults using a Robot car.

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Research Schedule†

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Step 2 Due date: Novemnber 15--> 22,2018†

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Step 3 Due date: 1/7 (Mon)†

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Step 4 Due date: 2/8 (Fri)†

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Step 5 Due date: 4/20†

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Step 6 Due date: 6/30 To be updated†

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Step 7 Due date: 8/30 To be uploaded†

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Step 8 Due date: 10/30 To be uploaded†

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Step 9 Due date: 12/30 To be uploaded†

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MS Thesis On-going Progress†

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RPS and RPR seminars†

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Robot Car source code†

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Ongoing Reports and Papers†

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Conferences†

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Reoports†

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References†

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