VLSI Design of Highly-Reliable NoC for 3D ICs
OASIS 3D Router Tutorials†
1. Synthesis with Design Compiler†
2. Place & Route with SoC Encounter†
3 LVS (Layout-Versus-Schematic)†
4 Post Layout Simulation:†
5 Pad Insertion†
 |
| Final Chip Layout |
Note: Replace the upper image with the real layout.
- Technology: 45nm CMOS Process
- Chip Size: ??
- Function: Router for 3D NoC System
- Frequency: ??
- Peak Performance: ??
- Power Dissipation: ??
- Completion Date: July 5th (expected)
Reference: MIPS processor Tutorials†
- Complete tutorial of MIPS processor prototyping on ASIC (in Japanese),
zip file
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