Design and Evaluation of 3D OASIS Router with Through-Silicon-Via (TSV)
Background (Problem Definition)†
During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.
One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research include a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations. Therefore, prototyping is an essential design phase for evaluating the performance of NoC architecture under real applications.
Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [1].
However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.
Research goal†
The main goals of this research are:
- 1. Study OASIS 3D Router Architecture
- 2. Design the Physical router using Design Compiler (for Synthesis) and SoC Enounter (for Place and route)
- 3. Verify the correctness at each step using ModelSim
- 4. Evaluate the performance of the final 3D Router (Area, Power, and Speed)
Design & Simulation Approach†
Fig.1 Design & Simulation Approach
Research Plan†
Step 1†
- Yuuki Tanaka, Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. slides.pdf, Thesis.pdf, technicalReport.pdf, slides.pdf
Step 2†
- Run on your machine these 2 tutorials (IN ORDER):
- OASIS 3D Router Design Tutorial, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.
Step 3†
Step 4†
Step 5†
References†
Verilog Code†
Papers, Theses†
- Yuuki Tanaka, Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. slides.pdf, Thesis.pdf, technicalReport.pdf, slides.pdf
- A. Ben Ahmed, On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu.
Thesis, slides
Updates:
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