OASIS-VP-Topic-1 の履歴(No.5)

• 履歴一覧
• 差分 を表示
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• OASIS-VP-Topic-1 へ行く。
  • 1 (2016-05-04 (水) 10:50:12)
  • 2 (2016-05-04 (水) 11:06:30)
  • 3 (2016-05-04 (水) 14:50:15)
  • 4 (2016-05-06 (金) 11:08:16)
  • 5 (2016-05-06 (金) 11:59:36)

OASIS-VP

Overview†

This topic is implementation and evaluation of a soft error resilience method for 3D Network-on-Chip.

Research Description†

There are two techniques includes in SER-OASIS:

• Error Correcting Code: using SECDED (single error correction, double error detection) code for correctting the flip bit of data.
• SER technique: adding redundant clock cycles to detect then correct the fault in NPC/SA pipeline stage.

Expected Output†

• Run and performance evaluate and extract the results.
• Understand the soft error resilience method for OASIS Network-on-Chip.
• Simulate error injection and performance of the Soft Error Resilience architecture.
• Compare the performance of the original OASIS and the Soft Error Resilience architecture.

References†

• Other references:

• [0] OASIS internal page: http://aslweb.u-aizu.ac.jp/aslint/index.php?OASIS

• [5] Source code: soft-ft.zip: soft error router; baseline-hlaft: OASIS router, tb.zip: Testbench files

• Other Documents: Link, Source code (OASIS)