![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
Leader: Murakami-1
Deep Neural Networks have been proved to be powerful tools for real world applications/tasks, such as pattern recognition, classification, regression, and prediction. However, simulating a large network in real-time requires high-performance machines or accelerators. Typical accelerators for large-scale NN accelerators use GPUs or ASIC chips. While ASICs deliver high performance, they lack the flexibility to reconfigure and hence are unable to adapt variation in the design and models employed. GPUs have better speedup over multi-core CPUs and good flexibility, but it lacks scalability to handle larger networks.
The goal of this research is to implement an FPGA-based Convolutional Neural Network for Pig Recognition.
Feed Forward Neural Networks (FFNN) when designed to work with floating point (FP) precision performs a large number of elementary products and sums. For each neuron of FFNN within the hidden layers, a non-linear function computation is required to determine the activation value of the neuron. Without efficient, dedicated FP hardware, such computations can create difficulties for the whole system performance of the system, hence making the design difficult to be used in critical applications like real-time systems.
The goal of this research is to implement a Feed Forward Neural Networks (FFNN) with floating point on FPGA. A real application, such as image recognition, should be demonstrated. The FFNN should be trained in Matlab environment and the Nios II/f (co cache) should be used for Altera FPGA prototyping. The Nios II ISA should be extended to have a Floating Point ALU.
Recently, machine learning algorithms have made immense progress, achieving accuracy close to human-level perception in various tasks, such as image-based search, and multi-category classification. However, most of the approaches rely on the availability of large datasets and the time-consuming off-line training to generate an accurate model, which are major limitations in applications with dynamic variations and personalized needs. In addition, the computational complexity of deep-learning and computer-vision algorithms still challenges the state-of-the-art computing platforms, especially when the application of interest is tightly constrained by the requirements of low-power, small latency, and high throughput.
The goal of this research work is to develop an efficient on-chip learning algorithm for NASH system.
