Eiji Yamashita の履歴(No.5)

• 履歴一覧
• 差分 を表示
• 現在との差分 を表示
• ソース を表示
• Eiji Yamashita へ行く。
  • 1 (2019-05-14 (火) 02:35:48)
  • 2 (2019-05-27 (月) 00:58:59)
  • 3 (2019-05-27 (月) 09:26:24)
  • 4 (2019-05-28 (火) 07:14:00)
  • 5 (2019-05-30 (木) 06:27:31)

Members-Internal

Research Bakground†

TBC

Research Goal†

• Design in hardware (Verilog, Cedence or/and Vivado Design Suite - Xilinx) a 64x64 Spiking Neuron Core (SNPC) based on crossbar and STDP (Spike-Timing-Dependent-Plasticity).
• Evalaute the hardware compelxity: Power, Area
• Run an Image Recogntion Benchmark/DS to verify the design

Research Scehdule

• Study previous GT thesis - LIF (Leaky Integrate and Fire) core

• https://adaptive.u-aizu.ac.jp/aslint/index.php?Theses#x191b349

• Make a presentaiotn on June 3, 2019, Time: 5 PM

References†

• LIF Neron

• Crossbar

• SNPC Specification

• STDP

• Simple LIF Neuron in Verilog (Developed and designed with Quartus II by Kanta Suzuki, BS 2017)