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High-performance, Scalable Nanophotonics On-chip Network for Many-core Systems

Research Motivation and Goal

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Electronic packet-switched on chip interconnects alleviate the problems of poor scalability, limited bandwidth, and high power consumption in traditional designs.

However, as feature sizes continue to shrink and as we are heading towards complex and large system design consisting of hundreds of PEs, traditional design approaches may not be enough for providing significant large bandwidth with low-power consumption.

Optical Network-on-Chip (ONoC) promises significant advantages over their electronic counterparts. In particular, they offer a potentially disruptive technology solution with fundamentally low power dissipation that remains independent of capacity while providing ultra-high throughput and minimal access latency.

My research goal is about the development of novel routing algorithms and architecture for high-throughput Si-Photonics NoC systems.

Detailed Research Schedule (Until October 31)

Topic TitleOverviewStart DateCompletion DateTarget Conf/JrnlDraft
Fully Optical Path setup Circuit switching Si-Photonic NoCPower, ETE and throughput evaluation against conventional hybrid PNoCs and PHENIC-IIJuly 3July 31IEEE Journal of Lightwave Technology
Thesis: First draftAugust 1August 20Thesis Content
Fully optical NoC based on multilayered switchA new switch will be proposed in order to eliminate previous drawbacks of PHENIC-II switch in term of crossingSeptember 1September 30
Thesis: Second draftOctober 1October 10Thesis Content

|BGDoctoral Diss


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