Vu Huy The の履歴(No.46) - ASL Wiki

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NASH: Neuro-inspired ArchitectureS in Hardware Project

Low-Power Scalable Spike-based Deep Neural Network System with Scalable Packet-Switched Network

Background, Research Goal, Achievement, etc.†

Research schedule†

Oct. to May 2017 †

Step 6: LIF spiking neuron model, proposal of a light-weight spiking learning algorithm for NASH†

Step 6.1: Study of CNN to SNN conversion
- Pre-trained SNN: training CNN, then applying learned weights into SNN. (7/3/2017, Time:2:00 PM) (pdf)
- Directly training a SNN, due date: July 24.
Step 6.2: Propose and evaluate learning method for SNN in hardware, due date: Aug. 28.

Step 7: A Scalable Fault-tolerant Multicast Routing Algorithm and Architectyure for Manycore Neuro-inpisred System†

Step 7.1: Study related works, (due date: Sept. 30)
Step 7.2: Propose a router architecture (due date: Oct. 10 6)
Step 7.3: Implement a whole network architecture (due date: Oct. 31)
Step 7.4: Evaluate the system and write a draft conf. paper (due date: Nov. 30 24)

Achievement†

On-going Conference and Jnl papers†

Article tentative title: Light-weight Fault-tolerant Multicast Routing Algorithm and Architecture for Manycore Neuro-inpisred System
- Target completion deadline of the 1st draft: November 24, 2017.
  - Pelase present your complete algorithm proposal by October 6, 2017

Submitted Conference papers†

Efficient Optimization and FPGA Accelerator Design for Deep Convolutional Neural Networks, Submitted on IEEE International Conference on Big Data and Smart Computing, 2018 (7/29/2017, Time:9:35 AM) (latex pdf)

Survey reports†

A Survey of Neuro-inspired Computing Systems (01/16/2017, Time:12:25 PM)(latex)

A Comparison between OASIS NoC and Conventional Wormhole NoC systems (12/8/2016, Time:14:08 PM ) (latex)

OASIS NoC Survey (11/29/2016, Time:15:55 PM) (latex)

NASH poster v1.0 (6/22/2017, Time:7:00 PM) (pptx,pdf)

NASH poster v2.0 (10/10/2017, Time:11:15 AM) (pptx,pdf)

CNNtoSNN survey (7/3/2017, Time:2:00 PM) (pdf)

FPGA price(xlsx)

Special NASH seminars †

April 2017
- FPGA BASED MULTI-CORE ARCHITECTURES FOR DEEP LEARNING NETWORKS, MS thesis, 2015.
  - 4/29/2017:Presentation pptx

May 2017

Spiking Deep Convolutional Neural Networks for Energy-Efficient Object Recognition

5/24/2017:Presentation pptx

June 2017

A reconfigurable on-line learning spiking neuromorphic processor comprising 256 neurons and 128K synapses, 2015.
- 5/24/2017:Presentation pptx
- (Based on this work: Brader,J.,Senn,W.,andFusi,S.(2007). Learning Real-World Stimuli in a Neural Network with Spike-Driven Synaptic Dynamics

July 2017
- A Study on Hardware Design for High-Performance Artificial Neural Network by using FPGA and NoC, PhD. Thesis, 2011
  - presentation.ppt

August 2017

Master Thesis "ZynqNet: An FPGA-Accelerated Embedded Convolutional Neural Network, MS thesis, 2016.
Source code
- presentation.ppt

Update Record†

5/29/2017: B.
3/24/2017: site updated, B.
3/10/2017: site updated, B.
3/6/2017: site updated, B.
2/17/2017: site update, B.
1/13/2017: added new ref, B.
12/8/2016: updated the research step deadlines, B.
12/6/2016: updated the research goal and the background, B.
Nov. 24,2016, updated Step 1.2, B.
Nov. 22,2016, Ref. added to Step 2, B.
Nov. 18, 2016, site updated, Ben
Nov. 11, 2016 - Research Schedule updated, B.
Nov. 8, 2016 - page created, B.