Takaya Hirai の履歴(No.4)

Design of a 2x2x2 OASIS Network-on-Chip System

Background†

During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.

One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research include a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations. Therefore, prototyping is an essential design phase for evaluating the performance of NoC architecture under real applications.

Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [1]. However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.

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Research goal†

The main goals of this research are:

1. Study OASIS 3D Router Architecture

2. Design the Physical router using Design Compiler (for Synthesis) and SoC Enounter (for Place and route)

3. Verify the correctness at each step using ModelSim

4. Evaluate the performance of the final 3D Router (Area, Power, and Speed)

5. Write a thesis

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Design & Simulation Approach†

Fig.1 Design & Simulation Approach

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Research Plan†

(1) -Run this Tutorial on your machine. OASIS 3D-Router Hardware Physical Design, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, July 8, 2014.

1.1 Understand 3D OASIS NoC Verilog HDL Code

(2) Design a 2x2x2 NoC System on FPGA

(3) Evaluation

(4) Thesis Writing

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References†

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Verilog Code†

3D OASIS NoC Verilog HDL Code

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Papers, Theses†

Yuuki Tanaka, Architecture and Design of an Efficient Router for OASIS 3D Network-on-Chip System, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, March 2015. slides.pdf, Thesis.pdf, technicalReport.pdf, slides.pdf

K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, Advanced Design Issues for OASIS Network-on-Chip Architecture, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.

OASIS 3D-Router Physical Design: I of III, Technical Report, Adaptive Systems Laboratory, Division of Computer Engineering, School of Computer Science and Engineering, University of Aizu, June 5, 2014.

3D-OASIS-Router Physical Design:Design and Simulation, Technical Report, April 1st, 2014.

Kenichi Mori, OASIS Network-on-Chip Prototyping on FPGA, '''Master's Thesis, Graduate School of Computer Science and Engineering,The University of Aizu, Feb. 2012.

K. Mori, A. Esch, A. Ben Abdallah, K. Kuroda, Advanced Design Issues for OASIS Network-on-Chip Architecture,IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.

A. Ben Ahmed, On the Design of a 3D Network-on-Chip for Many-core SoC, Master's Thesis, The University of Aizu. Thesis, slides

About TSV: Physical design of a 3D router: reducing the number of vertical connections and enabling asynchronous Operation

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