OASIS-8C System Design Manual の履歴(No.4)

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  • 1 (2015-06-04 (木) 08:20:35)
  • 2 (2015-06-19 (金) 05:12:03)
  • 3 (2015-07-15 (水) 05:01:07)
  • 4 (2015-08-09 (日) 05:58:33)
  • 5 (2015-08-10 (月) 03:24:51)

OASIS-8C System

Background†

TBU

Project Goal†

TBU

Hardware Specification†

Processor Implemenation†

Network Interface Implemenation†

In this task, a Network-Interface (NI) based on Okada's NI will be implemented. Above figure presents the system level architecture. The NI is connected with the network through its router. The NI also connects to the local bus-based system. List of documents:

• Okada's report
• Okada's mater slide
• Poster.

If you can, please answer these questions: link.

Network Implementation†

In this task, a Network-on-Chip will be established based on OASIS NoC router by Akram Ref.1. List of documents:

• Akram's master slide.
• Akram's mater thesis.

If you can, please answer these questions: link.

Application Implementation†

References†

• [Ref.1]: OASIS Network-on-Chip, Akram Ben Ahmed, Internal-link, Source-code.
• [Ref.2]: Network Inteface, R. Okada, Internal-link.
• [Ref.3]: FPGA manual (TBU).
• [Ref.4]: MIPS_MultiCycle.zip : file://///zxw001/PUBLIC/OASIS-8C/MIPS_MultiCycle.zip