M1 Akihito Kajikawa の履歴(No.4)

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• M1 Akihito Kajikawa へ行く。
  • 1 (2016-05-09 (月) 08:34:55)
  • 2 (2016-05-09 (月) 08:41:59)
  • 3 (2016-11-09 (水) 07:59:18)
  • 4 (2016-12-02 (金) 07:22:04)

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• OASIS-VP

• Members-Internal

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Research Background†

Research Goal†

Design and Evaluation of 4x4 Mesh-based NoC [for Real-time Image Processing Multicore System

Research Schedule†

Step 1 (Finished)†

• Design and evaluation of a single Router

Step 2 January 31, 2017 [#g690a5fb]†

• Design of a 4x4 OASIS NoC (without PEs)
• Study the complexity, bandwidth, and Latency

Step 3 February 28, 2017†

• Investigate and study SIFT Algorithm
  • Reference: SIFT Algorithm (in Japanese)

Step 4 April 30, 2017†

• Investigate SIFT Task Graph
• Investigate suitable PEs
• Investigate required hardware configuration

Step 5 June 30, 2017†

• Use Step 2 and integrate PEs, Memory, and NI.

Step 5 September 30, 2017†

• Evaluate the performance of the system.

Step 5 November 30, 2017†

• Debugging

Step 5 December 15 - Janury 8, 2018†

• Write MS thesis

References†

• GT

• Main references: Japanese spec: https://github.com/openrisc/or1200/blob/master/doc/openrisc1200_spec_0.7_jp.pdf

• Small MIPS Processor in Verilog

• Other Links

• OASIS-VP GDoc Spec (editable)
• SIFT Lecture (Video)
• SIFT Lecture (Japanese)
• SIFT Demo (Matlab)
• Tapeout (by Akram)