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During this last decade, 3D- Network-on-Chips (3D-NoCs) have been proposed as a promising solution for future systems on chip design. It offers more scalability, higher bandwidth, and less interconnect-power than the 2D-NoC architectures.
One of the major issues in 3D-NoC systems is how to verify the system correctness and integrity. 3D-NoC architecture research include a lot of trade-offs between topology, routing, flow control, buffer size, packet size, and other optimization techniques. It is difficult to analyze these trade-offs using only high-level simulations. Therefore, prototyping is an essential design phase for evaluating the performance of NoC architecture under real applications.
Previously, 3D-OASIS- NoC (3D-ONoC) has been designed. 3D-FTO showed great performance under real benchmarks and synthetic traffic patterns [1]. However, logic modules were connected to routers instead of real cores. This make the evaluation less accurate.
The main goal of this research is to evaluate and prototype 3D-ONoC with real cores (Nios II or MIPS processor). Okada's Network-Interface should be modified and adapted to be the interface between 3D-ONoC router and the chosen real core. The final goal of this research is to prototype the final design using Cadence SoC Encounter
