Michael Meyer の履歴(No.35)

Reliable 3D Photonic NoC for Many-core Systems

Research Motivation†

Current NoC technology is limited by the speed of their buses. In order to boost the throughput and reduce the power cost of these systems, we intend to implement a Photonic Network on Chip based around the 3D Oasis NoC design.

Most proposed networks are implemented with a dedicated photonic layer stacked on top of conventional electronic layer(s). However, to satisfies future applications with high-bandwidth requirements, single-layer typologies should be modified by increasing the number of wave-guides and MRs in the photonic layer. This technique may not be suitable because of the design limitation in a single photonic router, such as number of wave-guides spacing requirement, higher wave-guides crossing loses, etc. PHENIC implements multi-layer photonic network to deal with these problems.

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Research Goal†

Research on Reliable 3D Photonic NoC for Many-core Systems

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Research Plan†

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Step 1: Completed†

Study of OASIS 3D NoC
Survey about Photonic NoC main building blocks
Survey about Photonic Switches

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Step 2†

1.Development of FT switch for 3D PHENIC NoC System

2.Publication of an article entitled <Fault Tolerant 7x7 Optical Switch for 3D Hybrid Electrical-Photonic Network-on-Chip (PHENIC)

3.Survey about Fault Tolerant Photonic NoC. Due Date: ~~Nov. 30,~~, Dec. 28, 2014. (Please upload the survey .pdf file here)

4. TBC

5. TBC

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Step 3†

1. Run the OASIS-RV1 Tutorial

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Achievement (Jnl/Conference Publications, Technical Reports, Students Guidance, Public presentations)†

UPCOMING CONFERENCES: http://aslweb.u-aizu.ac.jp/aslint/index.php?Conferences

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Conference papers†

Michael Meyer, et al., Fault Tolerant 7x7 Optical Switch for 3D Hybrid Electrical-Photonic Network-on-Chip (PHENIC), Submitted to European Conference on Computer Systems (EuroSys), April 21-24, 2015, France (PDF), Latex.

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Journal papers†

None

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Technical Reports†

None

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Public Presentation @ Conferences†

None

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Related References†

10. TSV

9 A. Biberman et. al, first experimental bit-error rate validation of 12.5-Gb/s silicon modulator enabling photonic networks-on-chip, in IEEE /OSA Opt. Fiber Conf., 2010.

8. I. Datta et al., "Design Methodology for Optical Interconnect Topologies in NoCs With BER and Transmit Power Constraints," in IEEE/OSA JLT, 2014

7. Physical-Layer Modeling and System-Level Design of Chip-Scale Photonic Interconnection Networks, IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, VOL. 30, NO. 10, OCTOBER 2011

6. Recommended Reading 1

5. A complete electronic network interface architecture for global contention-free communication over emerging optical networks-on-chip, GLSVLSI '14 Proceedings of the 24th edition of the great lakes symposium on VLSI Pages 267-272,2014

4. OASIS Network-on-Chip Prototyping on FPGA, '''Master's Thesis, Graduate School of Computer Science and Engineering,The University of Aizu, Feb. 2012.

3. Architecture and Design of 3D Network-on-Chip, '''Master's Thesis, Graduate School of Computer Science and Engineering, The University of Aizu, Feb. 2012.

2. Advanced Design Issues for OASIS Network-on-Chip Architecture, IEEE Proc. of the 5th International Conference on Broadband, Wireless Computing, -Communication and Applications (BWCCA-2010), Nov. 2010, pp. 74-79.

1. Architecture and Design of Core Network Interface for Distributed Routing in OASIS NoC, Bachelor Thesis, School of Computer Science and Engineering, The University of Aizu, Feb. 2012, Ref. 16RO-GT09

. E-Books

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Related Projects†

PHENIC

OASIS

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OASIS 3D-Router†

Verilog Source Code
- 3D-OASIS NoC Verilog HDL Code

Physical Design
- OASIS 3D-Router Physical Design Tutorial, July 2014.

VLSI@ASL

Updates:

B., Nov. 9, 2014 - updated research progress tasks
Ben, Oct. 20, 2014 - added Ref. # 10.
Ben, July 17, 2014 - added Ref. 8 and 9, added OASIS Tutorial
Ben,27/05/14
Ben,20/05/14
Ben,12/04/14