FPGA Acceleration of Deep Convolutional Neural Network for FARM Monitoring
Research Schedule of 2019 - Please update it always according to your progress†
Step 1: Complete Soft implementation in Python (~3/17)†
- Do design space exploration(DSE) (Target accuracy is over 95%)
- DSE on Layer number of Fully Connection layer.
- DSE on bit precision.
- Current one is the 32-bit floating point -> 16 bit fixed point.
Step 2: Improve network for better accuracy (~3/17)†
- Apply some tuning techniques
- Collect more original data
- Data augmentation
- Fine Tuning
- Dropout (Regulation for avoiding overfitting.)
Step 3: Try re-implementation in C language. (3/26~4/2)†
- 32-bit floating point precision.
Step 4: Apply High-Level Synthesis for FPGA implementation. (4/3~4/15)†
- Apply HLS pragma for better execution ability in FPGA.
Always: Write paper for summarizing according to my progress.†
Research_2019†
RPS†
RPR†
Research_2018†
RPS†
RPR†
Research plan seminar†
CFS†
Background and Motivation†
Deep Neural Networks have been proved to be powerful tools for real world applications/tasks, such as pattern recognition,
classification, regression, and prediction. However, simulating a large network in real-time requires high-performance machines or accelerators.
Typical accelerators for large-scale NN accelerators use GPUs or ASIC chips. While ASICs deliver high performance, they lack the flexibility to reconfigure and hence are unable to adapt variation in the design and models employed. GPUs have better speedup over multi-core CPUs and good flexibility, but it lacks scalability to handle larger networks.
Goal and Expected output†
The goal of this research is to implement a Pig Face Recognition on FPGA using Deep Convolution Neural Network to be integrated in OASIS-FMS1 system.
References†
![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
