Cadence Design Tutorials, 2020†
genus - Synthesis†
innovus -Place and Route†
virtuoso - Schematic and simulation†
Tutorial from cadence Website
Refreences†
Maven Silicon
Xilinx Lisence and Tool Installation Instruction (created by R. Murakami, Oct. 24, 2017)†
Administrator: Vu(d8182106), R.Murkami(m5211126)†
Description†
- XILINX VIVADO LICENSE for university program links
- LICENSES are created dynamically(floating / Node-Locked one). If you want to use VIVADO license you can ask administrator to create LICENSE. [#i6d95cf6]
Necessary information for creating are ...†
- Host name
- Operating system
- Host ID type(e.g. Ethernet MAC)
- Host ID value
User records†
| User name | Created Date | License type |
| Ryunosuke Murakami | 2017/10/24 | Node-Locked |
| | |
| | |
OASIS NoC Router Tutorials†
OASIS-RV1 Chip Layout. JUly 7, 2014.
- Technology: 45nm CMOS Process
- Chip Size: 2.205X2.220 (micron)
- Function: Router for 3D NoC System
- Frequency: 0.91 GHZ Confirmed
- Supply voltage: 1.1V
- Power Dissipation: 222.387 uW
- Number of Pins: 557
- Completion Date: July 5th (expected)
1. Synthesis with Design Compiler†
2. Place & Route with SoC Encounter†
3 Design Checking: LVS (Layout-Versus-Schematic) and DRC (Design-Rule Check)†
4 Post Layout Simulation:†
5 Pad Insertion†
6. Chip Submission†
- PDF, PPT, Completion Date: July 15th
PHENIC Control Router†
1. Synthesis with Design Compiler†
2. Place & Route with SoC Encounter†
3 Design Checking: LVS (Layout-Versus-Schematic) and DRC (Design-Rule Check)†
4 Post Layout Simulation:†
5 Pad Insertion†
Reference: MIPS processor Tutorials†
- Complete tutorial of MIPS processor prototyping on ASIC (in Japanese),
zip file
How to Login and use VDEC tools on zxp035†
- To use VDEC tools on zxp035 machine type the following comand in your terminal
- Password : blm2011
- design_vision (to use Design Compiler)
- velocity (to use SoC Encounter)
- simvision (to use Simvision)
Registerd IPs @ with VDEC Server†
Links†
![[PukiWiki]](image/pukiwiki.png "[PukiWiki]")
